VHDL Code for Register File: Syntax, Example, and Tips

A register file in VHDL is a collection of registers accessed by read and write addresses. You define it using an array of std_logic_vector and control read/write operations with clock and enable signals. The code includes ports for data input, output, addresses, write enable, and clock.

Syntax

A register file in VHDL is typically defined as an array of registers with read and write ports. Key parts include:

• Entity ports: data input, data output, read/write addresses, write enable, and clock.
• Architecture: defines the register array and processes for synchronous write and asynchronous read.

vhdl

entity RegisterFile is
    generic (
        DATA_WIDTH : integer := 8;
        ADDR_WIDTH : integer := 4
    );
    port (
        clk       : in  std_logic;
        we        : in  std_logic;
        waddr     : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        raddr     : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        wdata     : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        rdata     : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end RegisterFile;

architecture Behavioral of RegisterFile is
    type reg_array is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
    signal regs : reg_array := (others => (others => '0'));
begin
    process(clk) is
    begin
        if rising_edge(clk) then
            if we = '1' then
                regs(to_integer(unsigned(waddr))) <= wdata;
            end if;
        end if;
    end process;

    rdata <= regs(to_integer(unsigned(raddr)));
end Behavioral;

Example

This example shows a 16x8 register file with synchronous write and asynchronous read. It demonstrates writing data to a register on the rising clock edge when we is high, and reading data from a register asynchronously.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity RegisterFile is
    generic (
        DATA_WIDTH : integer := 8;
        ADDR_WIDTH : integer := 4
    );
    port (
        clk       : in  std_logic;
        we        : in  std_logic;
        waddr     : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        raddr     : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        wdata     : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        rdata     : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end RegisterFile;

architecture Behavioral of RegisterFile is
    type reg_array is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
    signal regs : reg_array := (others => (others => '0'));
begin
    process(clk) is
    begin
        if rising_edge(clk) then
            if we = '1' then
                regs(to_integer(unsigned(waddr))) <= wdata;
            end if;
        end if;
    end process;

    rdata <= regs(to_integer(unsigned(raddr)));
end Behavioral;

Common Pitfalls

Common mistakes when coding a register file in VHDL include:

• Forgetting to convert std_logic_vector addresses to integers using to_integer(unsigned()).
• Writing data asynchronously instead of on the clock edge, which can cause timing issues.
• Not initializing the register array, leading to unknown values.
• Using blocking assignments instead of signal assignments inside processes.

Always use synchronous write inside a clocked process and asynchronous read outside the process.

vhdl

wrong: process(clk) is
begin
    if we = '1' then
        regs(to_integer(unsigned(waddr))) <= wdata; -- asynchronous write (wrong)
    end if;
end process;

right: process(clk) is
begin
    if rising_edge(clk) then
        if we = '1' then
            regs(to_integer(unsigned(waddr))) <= wdata; -- synchronous write (correct)
        end if;
    end if;
end process;

Quick Reference

Tips for writing VHDL register files:

• Use std_logic_vector for data and address ports.
• Convert addresses to integers with to_integer(unsigned(addr)) for indexing.
• Write data only on rising clock edge with write enable.
• Read data asynchronously by assigning output directly from the register array.
• Initialize registers to zero to avoid unknown states.

Key Takeaways

Define register file as an array of std_logic_vector indexed by integer addresses.

Perform synchronous writes inside a clocked process with write enable control.

Read data asynchronously by direct assignment from the register array.

Always convert std_logic_vector addresses to integers for indexing.

Initialize registers to known values to avoid unknown states.