Concurrent vs Sequential in VHDL: Key Differences and Usage

In VHDL, concurrent statements run simultaneously and describe hardware behavior that happens in parallel, while sequential statements run one after another inside processes or subprograms, describing step-by-step operations. Concurrent code models real hardware wiring, and sequential code models ordered logic inside that hardware.

Quick Comparison

This table summarizes the main differences between concurrent and sequential statements in VHDL.

Aspect	Concurrent Statements	Sequential Statements
Execution	All run in parallel	Run one after another
Location	Outside processes or inside architecture	Inside processes, functions, or procedures
Purpose	Describe hardware connections and parallel behavior	Describe ordered operations and control flow
Examples	Signal assignments, component instantiations	Variable assignments, if-else, loops
Sensitivity	Triggered by signal changes automatically	Triggered by process sensitivity list or wait statements
Hardware Model	Models physical hardware wiring	Models behavior inside hardware blocks

Key Differences

Concurrent statements in VHDL represent hardware elements that operate simultaneously, just like real circuits where many signals change at the same time. These statements are written directly in the architecture body and are always active, reacting to changes in signals without explicit control flow.

On the other hand, sequential statements appear inside processes, functions, or procedures. They execute in a defined order, one after another, similar to instructions in a program. Sequential code uses variables, loops, and conditional statements to describe step-by-step behavior within a hardware block.

In summary, concurrent code models the parallel nature of hardware wiring, while sequential code models the internal logic and control flow inside hardware components.

Code Comparison

Here is an example showing a simple 2-input AND gate implemented using concurrent statements in VHDL.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;  -- concurrent signal assignment
end Behavioral;

Output

When inputs A and B are both '1', output Y is '1'; otherwise, Y is '0'.

Sequential Equivalent

The same AND gate behavior implemented inside a process using sequential statements.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    process(A, B)  -- sensitivity list
    begin
        if (A = '1') and (B = '1') then
            Y <= '1';
        else
            Y <= '0';
        end if;
    end process;
end Behavioral;

Output

When inputs A and B are both '1', output Y is '1'; otherwise, Y is '0'.

When to Use Which

Choose concurrent statements when you want to describe simple hardware connections and parallel signal assignments clearly and directly. They are best for combinational logic and structural descriptions.

Use sequential statements inside processes when you need ordered control flow, such as implementing state machines, counters, or complex conditional logic. Sequential code allows you to write step-by-step behavior that depends on previous steps.

In practice, most VHDL designs combine both: concurrent statements for wiring and simple logic, and sequential statements inside processes for complex behavior.

Key Takeaways

Concurrent statements run in parallel and model hardware wiring directly.

Sequential statements run in order inside processes and model internal logic flow.

Use concurrent code for simple combinational logic and wiring.

Use sequential code for control flow, state machines, and complex behavior.

Most VHDL designs combine both concurrent and sequential styles.