VHDL Code for Gray Code Counter: Syntax and Example

A Gray code counter in VHDL is a sequential circuit that counts in Gray code sequence, where only one bit changes at a time. You can implement it using a process triggered by a clock, updating the output with the next Gray code value on each clock cycle.

Syntax

The basic syntax for a Gray code counter in VHDL includes defining an entity with input clock and reset signals, and an output for the Gray code count. Inside the architecture, a process sensitive to the clock and reset updates the Gray code output on each rising clock edge.

• entity: Declares inputs and outputs.
• architecture: Contains the logic.
• process: Runs on clock and reset events.
• signal: Holds the current binary count internally.
• Gray code conversion: Done by XORing the binary count with its right-shifted version.

vhdl

entity gray_counter is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        gray  : out std_logic_vector(3 downto 0)
    );
end gray_counter;

architecture Behavioral of gray_counter is
    signal bin_count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            bin_count <= (others => '0');
        elsif rising_edge(clk) then
            bin_count <= bin_count + 1;
        end if;
    end process;

    gray <= std_logic_vector(bin_count xor (bin_count(3 downto 1) & '0'));
end Behavioral;

Example

This example shows a 4-bit Gray code counter that increments on each rising clock edge and resets asynchronously. The output gray gives the Gray code equivalent of the binary count.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gray_counter is
    Port (
        clk   : in  std_logic;
        reset : in  std_logic;
        gray  : out std_logic_vector(3 downto 0)
    );
end gray_counter;

architecture Behavioral of gray_counter is
    signal bin_count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            bin_count <= (others => '0');
        elsif rising_edge(clk) then
            bin_count <= bin_count + 1;
        end if;
    end process;

    gray <= std_logic_vector(bin_count xor (bin_count(3 downto 1) & '0'));
end Behavioral;

Output

On each rising clock edge, the output 'gray' cycles through Gray code sequence: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000, then repeats.

Common Pitfalls

Common mistakes when writing a Gray code counter in VHDL include:

• Not resetting the binary counter properly, causing unpredictable output.
• Incorrect Gray code conversion logic, such as missing the XOR operation.
• Using asynchronous reset without proper sensitivity list, leading to simulation mismatches.
• Forgetting to use rising_edge(clk) for synchronous counting.

Always verify the Gray code sequence output matches expected values.

vhdl

---- Wrong Gray code conversion example ----
-- gray <= std_logic_vector(bin_count xor bin_count(2 downto 0)); -- Incorrect slicing

---- Correct Gray code conversion ----
gray <= std_logic_vector(bin_count xor (bin_count(3 downto 1) & '0'));

Quick Reference

• Use unsigned type for binary counting.
• Convert binary to Gray code with gray = binary XOR (binary shifted right by 1).
• Reset the counter asynchronously for predictable start.
• Use rising_edge(clk) for synchronous updates.
• Test output sequence to confirm Gray code correctness.

Key Takeaways

Implement Gray code counters by incrementing a binary count and converting it using XOR with its right-shifted self.

Always reset the binary counter properly to avoid unpredictable outputs.

Use synchronous clock edge detection with rising_edge(clk) for reliable counting.

Verify the Gray code output sequence matches the expected pattern.

Use unsigned types and proper slicing for clean and correct Gray code conversion.