How to Write Process in VHDL: Syntax and Example

In VHDL, a process is written using the process keyword followed by an optional sensitivity list and a block of sequential statements enclosed by begin and end process;. It models sequential behavior and reacts to signals in the sensitivity list.

Syntax

A VHDL process block starts with the keyword process, optionally followed by a sensitivity list in parentheses. Inside the process, you write sequential statements between begin and end process;. The sensitivity list tells the process which signals to watch for changes.

• process (sensitivity_list): Declares the process and signals it reacts to.
• begin: Starts the sequential statement section.
• sequential statements: Code that runs when a signal in the sensitivity list changes.
• end process;: Ends the process block.

vhdl

process (clk, reset)
begin
    if reset = '1' then
        -- reset logic
    elsif rising_edge(clk) then
        -- sequential logic
    end if;
end process;

Example

This example shows a simple clocked process that resets and increments a counter on the rising edge of a clock signal.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
    port (
        clk   : in std_logic;
        reset : in std_logic;
        count : out unsigned(3 downto 0)
    );
end entity;

architecture Behavioral of counter is
    signal cnt : unsigned(3 downto 0) := (others => '0');
begin
    process (clk, reset)
    begin
        if reset = '1' then
            cnt <= (others => '0');
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
        end if;
    end process;

    count <= cnt;
end Behavioral;

Common Pitfalls

Common mistakes when writing VHDL processes include:

• Forgetting to include all signals that the process depends on in the sensitivity list, which can cause simulation mismatches.
• Using combinational logic inside a process without a complete sensitivity list, leading to latches.
• Mixing blocking and non-blocking assignments (VHDL uses only signal assignments with <=).

Always ensure your sensitivity list matches the signals read in the process or use process(all) in VHDL-2008 for combinational logic.

vhdl

Wrong:
process(clk)
begin
    if reset = '1' then
        q <= '0'; -- reset signal not in sensitivity list
    elsif rising_edge(clk) then
        q <= d;
    end if;
end process;

Right:
process(clk, reset)
begin
    if reset = '1' then
        q <= '0';
    elsif rising_edge(clk) then
        q <= d;
    end if;
end process;

Quick Reference

Element	Description
process (sensitivity_list)	Starts a process that reacts to signals in the list
begin	Starts the sequential code block
if ... elsif ... end if;	Conditional statements inside the process
signal <= value;	Signal assignment inside process
end process;	Ends the process block

Key Takeaways

A VHDL process models sequential logic triggered by signals in its sensitivity list.

Always include all signals read inside the process in the sensitivity list to avoid simulation issues.

Use if rising_edge(clk) to detect clock edges inside a process.

Sequential statements inside a process run one after another when triggered.

For combinational logic, ensure the sensitivity list is complete or use VHDL-2008 process(all).