VHDL Code for Simple Calculator: Syntax and Example

A simple calculator in VHDL uses a case statement inside a process to select operations like add, subtract, multiply, and divide based on an input opcode. The calculator takes two input numbers and an operation code, then outputs the result accordingly.

Syntax

The basic syntax for a calculator in VHDL involves defining inputs for two numbers and an operation code, then using a process block with a case statement to select the operation. The result is assigned to an output signal.

• entity: Defines inputs and outputs.
• architecture: Contains the logic.
• process: Runs when inputs change.
• case: Chooses operation based on opcode.

vhdl

entity Calculator is
    Port (
        A       : in  integer;
        B       : in  integer;
        OpCode  : in  std_logic_vector(1 downto 0); -- 2-bit operation code
        Result  : out integer
    );
end Calculator;

architecture Behavioral of Calculator is
begin
    process(A, B, OpCode)
    begin
        case OpCode is
            when "00" =>
                Result <= A + B; -- Addition
            when "01" =>
                Result <= A - B; -- Subtraction
            when "10" =>
                Result <= A * B; -- Multiplication
            when "11" =>
                if B /= 0 then
                    Result <= A / B; -- Division
                else
                    Result <= 0; -- Avoid division by zero
                end if;
            when others =>
                Result <= 0;
        end case;
    end process;
end Behavioral;

Example

This example shows a simple calculator that adds, subtracts, multiplies, or divides two integers based on a 2-bit operation code. It handles division by zero by outputting zero.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Calculator is
    Port (
        A       : in  integer;
        B       : in  integer;
        OpCode  : in  std_logic_vector(1 downto 0);
        Result  : out integer
    );
end Calculator;

architecture Behavioral of Calculator is
begin
    process(A, B, OpCode)
    begin
        case OpCode is
            when "00" =>
                Result <= A + B;
            when "01" =>
                Result <= A - B;
            when "10" =>
                Result <= A * B;
            when "11" =>
                if B /= 0 then
                    Result <= A / B;
                else
                    Result <= 0;
                end if;
            when others =>
                Result <= 0;
        end case;
    end process;
end Behavioral;

Output

For inputs A=10, B=5, OpCode="00" (add), Result=15
For inputs A=10, B=5, OpCode="01" (subtract), Result=5
For inputs A=10, B=5, OpCode="10" (multiply), Result=50
For inputs A=10, B=5, OpCode="11" (divide), Result=2

Common Pitfalls

Common mistakes when writing a VHDL calculator include:

• Not handling division by zero, which can cause simulation errors.
• Using std_logic_vector for arithmetic without conversion to integer.
• Forgetting to include all inputs in the process sensitivity list.
• Not covering all case options, leading to unexpected results.

vhdl

Wrong way (no division by zero check):
process(A, B, OpCode)
begin
    case OpCode is
        when "11" =>
            Result <= A / B; -- Risky if B=0
        when others =>
            Result <= 0;
    end case;
end process;

Right way (with check):
process(A, B, OpCode)
begin
    case OpCode is
        when "11" =>
            if B /= 0 then
                Result <= A / B;
            else
                Result <= 0;
            end if;
        when others =>
            Result <= 0;
    end case;
end process;

Quick Reference

Calculator operation codes:

OpCode	Operation
"00"	Addition (A + B)
"01"	Subtraction (A - B)
"10"	Multiplication (A * B)
"11"	Division (A / B), with zero check

Key Takeaways

Use a process with a case statement to select calculator operations based on an opcode.

Always check for division by zero to avoid errors.

Include all inputs in the process sensitivity list for correct simulation.

Use integer types for arithmetic or convert std_logic_vector properly.

Cover all possible opcode values with a when others clause.