Two Process vs One Process FSM in VHDL: Key Differences and Usage

In VHDL, a two process FSM separates state transitions and output logic into two distinct processes, improving clarity and modularity. A one process FSM combines both state transitions and output logic in a single process, making it more compact but sometimes harder to read and maintain.

Quick Comparison

This table summarizes the main differences between two process and one process FSM designs in VHDL.

Aspect	Two Process FSM	One Process FSM
Structure	Separate processes for state transitions and output logic	Single process handles both state transitions and output logic
Readability	Clear separation improves readability	More compact but can be harder to follow
Modularity	Easier to modify outputs or states independently	Less modular, changes affect whole process
Synthesis	Equivalent hardware, no performance difference	Equivalent hardware, no performance difference
Debugging	Simpler to isolate state or output issues	Harder to isolate issues due to combined logic
Usage	Preferred for complex FSMs or teaching	Common for simple FSMs or quick designs

Key Differences

A two process FSM in VHDL uses one process to handle the state register and state transitions triggered by clock edges, and a separate combinational process to determine outputs based on the current state. This clear separation helps beginners understand the flow of states and outputs independently.

In contrast, a one process FSM combines both the state update and output logic inside a single clocked process. This approach reduces code size but mixes sequential and combinational logic, which can make the code harder to read and maintain, especially for larger FSMs.

Both styles synthesize to the same hardware, so the choice is mostly about code clarity and maintainability. Two process FSMs are often preferred in teaching and complex designs, while one process FSMs are common in simpler or quick implementations.

Code Comparison

Here is an example of a two process FSM in VHDL that cycles through three states and sets outputs accordingly.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity two_process_fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           out_signal : out STD_LOGIC_VECTOR(1 downto 0));
end two_process_fsm;

architecture Behavioral of two_process_fsm is
    type state_type is (S0, S1, S2);
    signal state, next_state : state_type;
begin
    -- Process 1: State register
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    -- Process 2: Next state and output logic
    process(state)
    begin
        case state is
            when S0 =>
                next_state <= S1;
                out_signal <= "00";
            when S1 =>
                next_state <= S2;
                out_signal <= "01";
            when S2 =>
                next_state <= S0;
                out_signal <= "10";
            when others =>
                next_state <= S0;
                out_signal <= "00";
        end case;
    end process;
end Behavioral;

Output

The FSM cycles states S0 -> S1 -> S2 -> S0 with outputs 00, 01, 10 respectively on each clock cycle.

One Process FSM Equivalent

This example shows the same FSM implemented with a single process handling both state transitions and outputs.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity one_process_fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           out_signal : out STD_LOGIC_VECTOR(1 downto 0));
end one_process_fsm;

architecture Behavioral of one_process_fsm is
    type state_type is (S0, S1, S2);
    signal state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S0;
            out_signal <= "00";
        elsif rising_edge(clk) then
            case state is
                when S0 =>
                    state <= S1;
                    out_signal <= "00";
                when S1 =>
                    state <= S2;
                    out_signal <= "01";
                when S2 =>
                    state <= S0;
                    out_signal <= "10";
                when others =>
                    state <= S0;
                    out_signal <= "00";
            end case;
        end if;
    end process;
end Behavioral;

Output

The FSM cycles states S0 -> S1 -> S2 -> S0 with outputs 00, 01, 10 respectively on each clock cycle.

When to Use Which

Choose a two process FSM when you want clear separation between state transitions and output logic, which helps with readability, debugging, and maintenance, especially for complex designs or when teaching FSM concepts.

Choose a one process FSM for simpler or smaller FSMs where compact code is preferred and the design is straightforward, as it reduces the number of processes and can be quicker to write.

Key Takeaways

Two process FSMs separate state and output logic for clearer, modular code.

One process FSMs combine logic for compactness but can be harder to read.

Both styles synthesize to the same hardware with no performance difference.

Use two process FSMs for complex or educational designs.

Use one process FSMs for simple, quick implementations.