How to Use Block in VHDL: Syntax and Examples

In VHDL, a block groups signals and statements together, allowing you to organize code and apply local declarations or conditions. You use block with an optional label and an optional when condition to control execution. This helps structure designs clearly and manage signal scopes.

Syntax

The block statement syntax includes an optional label, an optional when condition, and a sequence of declarations and statements inside begin and end block. It looks like this:

• label: Names the block for reference.
• when condition: Optional condition to enable the block.
• declarations: Signals or components local to the block.
• statements: Concurrent statements executed if the block is active.

vhdl

label_name: block [when condition] is
    -- local declarations
begin
    -- concurrent statements
end block label_name;

Example

This example shows a block named my_block with a local signal and a conditional when clause. The block is active only when enable is '1'. Inside, it assigns out_signal based on in_signal.

vhdl

architecture Behavioral of example_entity is
    signal in_signal : std_logic;
    signal out_signal : std_logic;
    signal enable : std_logic := '1';
begin
    my_block: block when enable = '1' is
        signal temp_signal : std_logic;
    begin
        temp_signal <= in_signal;
        out_signal <= temp_signal;
    end block my_block;
end Behavioral;

Output

No direct output; the block conditionally assigns signals when enable = '1'.

Common Pitfalls

Common mistakes when using block include:

• Forgetting to label the block, which can cause confusion or errors when ending the block.
• Misusing the when condition syntax or placing it incorrectly.
• Declaring signals inside the block but trying to use them outside its scope.

Always ensure the block label matches at the start and end, and use the when condition properly to control block activation.

vhdl

wrong_block: block
    signal temp : std_logic;
begin
    -- Trying to use temp outside this block will cause errors
end block wrong_block;

-- Correct usage:
correct_block: block when enable = '1' is
    signal temp : std_logic;
begin
    -- temp is local and block runs only if enable = '1'
end block correct_block;

Quick Reference

Block statement quick tips:

• Use a label to name your block for clarity.
• Use when to conditionally enable the block.
• Declare signals inside the block to limit their scope.
• Blocks help organize complex designs and control signal visibility.

Key Takeaways

Use block to group signals and statements with optional local declarations.

Label your block and match the label at the end for clarity and correctness.

Use the when clause to conditionally activate the block.

Signals declared inside a block are local and not visible outside it.

Blocks help organize VHDL code and manage signal scope effectively.