VhdlHow-ToBeginner · 4 min read

How to Use Xilinx Vivado for VHDL Development

To use Xilinx Vivado for VHDL, start by creating a new project and adding your VHDL source files. Then, simulate your design using Vivado's built-in simulator, synthesize the design, and finally implement it on your FPGA device.

📐

Syntax

In Vivado, VHDL code follows the standard VHDL syntax structure:

Library and use clauses: Import necessary libraries.
Entity: Defines the interface (inputs and outputs).
Architecture: Describes the internal behavior or structure.

Vivado supports VHDL-93 and later standards.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MyModule is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           out_signal : out STD_LOGIC);
end MyModule;

architecture Behavioral of MyModule is
begin
    process(clk, rst)
    begin
        if rst = '1' then
            out_signal <= '0';
        elsif rising_edge(clk) then
            out_signal <= not out_signal;
        end if;
    end process;
end Behavioral;

💻

Example

This example shows a simple VHDL module that toggles an output signal on each rising clock edge, with reset support. You can create this in Vivado, simulate it, and then synthesize for FPGA implementation.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Toggle is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           led : out STD_LOGIC);
end Toggle;

architecture Behavioral of Toggle is
begin
    process(clk, rst)
    begin
        if rst = '1' then
            led <= '0';
        elsif rising_edge(clk) then
            led <= not led;
        end if;
    end process;
end Behavioral;

Output

Simulation waveform shows 'led' toggling between '0' and '1' on each rising clock edge after reset is released.

⚠️

Common Pitfalls

Not setting the correct top module: Vivado needs the top-level entity set correctly to synthesize.
Forgetting to add all source files: Missing files cause errors during synthesis or simulation.
Ignoring clock constraints: Without proper constraints, timing analysis will fail.
Using unsupported VHDL features: Some advanced VHDL constructs may not be supported or synthesizable.

Always check the Vivado messages and warnings carefully.

vhdl

---- Wrong: Missing top module setting ----
-- Vivado synthesis error: "No top module specified"

---- Right: Set top module in project settings ----
-- Go to Project Settings > General > Top Module and select your top entity name.

📊

Quick Reference

Steps to use Vivado for VHDL:

Create a new project and select your FPGA device.
Add your VHDL source files to the project.
Set the top module (top entity) in project settings.
Write or import your VHDL code.
Run simulation to verify behavior.
Run synthesis to convert code to hardware logic.
Run implementation to map design to FPGA resources.
Generate bitstream to program the FPGA.

✅

Key Takeaways

Start by creating a Vivado project and adding your VHDL files.

Always set the correct top-level entity before synthesis.

Use Vivado's simulator to verify your VHDL design behavior.

Apply proper constraints for clocks and pins to ensure correct implementation.

Check Vivado messages carefully to avoid common errors.