How to Write File in VHDL Testbench: Simple Guide

In a VHDL testbench, you can write to a file using the textio package by declaring a file variable, opening it in write mode, and using write and writeline procedures to output data. This allows you to save simulation results or logs to an external text file.

Syntax

To write to a file in VHDL testbench, you use the textio package. You declare a file variable with mode write, then use write to add data to a line buffer and writeline to write that line to the file.

• file file_variable : text open write_mode is "filename"; declares and opens the file.
• variable line_var : line; declares a line buffer to hold text before writing.
• write(line_var, data); adds data to the line buffer.
• writeline(file_variable, line_var); writes the buffered line to the file.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity dummy is
end entity;

architecture behavior of dummy is
begin
  -- no hardware
end architecture;

Example

This example shows a simple VHDL testbench that writes some text and numbers to a file named output.txt. It demonstrates opening the file, writing lines, and closing it automatically at the end of simulation.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb_write_file is
end entity;

architecture testbench of tb_write_file is
  file output_file : text open write_mode is "output.txt";
begin
  process
    variable line_buffer : line;
    variable i : integer := 0;
  begin
    for i in 1 to 5 loop
      write(line_buffer, string'("Count = "));
      write(line_buffer, i);
      writeline(output_file, line_buffer);
    end loop;
    wait;
  end process;
end architecture;

Output

Content of output.txt after simulation:
Count = 1
Count = 2
Count = 3
Count = 4
Count = 5

Common Pitfalls

Common mistakes when writing files in VHDL testbenches include:

• Not declaring the file with open write_mode which prevents writing.
• Forgetting to use a line variable to buffer text before writing.
• Using write without writeline, so data never actually goes to the file.
• Trying to write to a file in synthesis code instead of testbench (file I/O is for simulation only).

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb_wrong is
end entity;

architecture testbench of tb_wrong is
  -- Missing open write_mode
  file output_file : text open read_mode is "output.txt";
begin
  process
    variable line_buffer : line;
  begin
    write(line_buffer, string'("Hello"));
    -- Missing writeline call, so nothing written
    wait;
  end process;
end architecture;

Quick Reference

Remember these key points when writing files in VHDL testbenches:

• Use file with open write_mode to create or overwrite files.
• Use a line variable to collect text before writing.
• Use write to add data to the line, then writeline to save it.
• File writing works only in simulation, not in hardware synthesis.

Key Takeaways

Use the std.textio package to write files in VHDL testbenches.

Declare files with open write_mode and use line buffers for writing.

Always call writeline to output buffered data to the file.

File writing is for simulation only and not supported in synthesis.

Check file paths and permissions if files do not appear after simulation.