How to Compile and Simulate VHDL Code Quickly

To compile and simulate VHDL code, first use a VHDL compiler like ghdl -a to analyze your source files, then elaborate the design with ghdl -e, and finally run the simulation using ghdl -r. This process checks your code for errors and lets you observe its behavior before hardware implementation.

Syntax

Here is the basic syntax to compile and simulate VHDL code using the ghdl tool:

• ghdl -a filename.vhdl: Analyze (compile) the VHDL source file.
• ghdl -e entity_name: Elaborate the top-level entity to prepare for simulation.
• ghdl -r entity_name: Run the simulation of the elaborated design.

Replace filename.vhdl with your VHDL file name and entity_name with the top module's entity name.

bash

ghdl -a my_design.vhdl
ghdl -e my_entity
ghdl -r my_entity

Example

This example shows a simple VHDL design of a 2-input AND gate and how to compile and simulate it using ghdl. The simulation prints the output values to the console.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port(
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end entity and_gate;

architecture behavior of and_gate is
begin
    y <= a and b;
end architecture behavior;

-- Testbench
entity tb_and_gate is
end entity tb_and_gate;

architecture test of tb_and_gate is
    signal a, b, y : std_logic := '0';
begin
    uut: entity work.and_gate
        port map(a => a, b => b, y => y);

    process
    begin
        a <= '0'; b <= '0'; wait for 10 ns;
        report "a=0 b=0 y=" & std_logic'image(y);
        a <= '0'; b <= '1'; wait for 10 ns;
        report "a=0 b=1 y=" & std_logic'image(y);
        a <= '1'; b <= '0'; wait for 10 ns;
        report "a=1 b=0 y=" & std_logic'image(y);
        a <= '1'; b <= '1'; wait for 10 ns;
        report "a=1 b=1 y=" & std_logic'image(y);
        wait;
    end process;
end architecture test;

Output

tb_and_gate.vhdl:20: note: a=0 b=0 y='0'
tb_and_gate.vhdl:22: note: a=0 b=1 y='0'
tb_and_gate.vhdl:24: note: a=1 b=0 y='0'
tb_and_gate.vhdl:26: note: a=1 b=1 y='1'

Common Pitfalls

Common mistakes when compiling and simulating VHDL code include:

• Forgetting to analyze all dependent files before elaboration.
• Using the wrong entity name in the ghdl -e and ghdl -r commands.
• Not including a testbench to simulate inputs and observe outputs.
• Ignoring simulation output messages that help debug logic errors.

Always check that your testbench signals are properly driven and that wait statements are used to allow simulation time to advance.

bash

Wrong:
ghdl -e wrong_entity

Right:
ghdl -e correct_entity

Quick Reference

Command	Purpose
ghdl -a filename.vhdl	Analyze (compile) VHDL source file
ghdl -e entity_name	Elaborate top-level entity for simulation
ghdl -r entity_name	Run the simulation
ghdl --wave=filename.ghw	Generate waveform file for viewing
gtkwave filename.ghw	Open waveform viewer to analyze signals

Key Takeaways

Use 'ghdl -a' to compile your VHDL files before simulation.

Elaborate your top entity with 'ghdl -e' to prepare for running.

Run simulation with 'ghdl -r' and observe output or waveforms.

Include a testbench to provide inputs and check outputs during simulation.

Check simulation messages carefully to catch errors early.