VHDL Code for SR Flip Flop: Syntax and Example

An SR flip flop in VHDL can be coded using a process block sensitive to S, R, and CLK signals. The output Q sets to 1 when S is 1, resets to 0 when R is 1, and holds its state otherwise.

Syntax

The SR flip flop in VHDL is typically described inside a process block that reacts to changes in the S (Set), R (Reset), and CLK (Clock) signals. Inside the process, if statements check the inputs to set or reset the output Q.

• S: Set input, sets Q to 1.
• R: Reset input, resets Q to 0.
• CLK: Clock input, triggers the flip flop on rising edge.
• Q: Output signal holding the flip flop state.

vhdl

process(CLK)
begin
    if rising_edge(CLK) then
        if S = '1' and R = '0' then
            Q <= '1';
        elsif R = '1' and S = '0' then
            Q <= '0';
        elsif S = '0' and R = '0' then
            Q <= Q; -- hold state
        else
            Q <= 'X'; -- invalid state when S=R=1
        end if;
    end if;
end process;

Example

This example shows a complete VHDL entity and architecture for an SR flip flop. It uses a clock and two inputs S and R. The output Q changes according to the SR flip flop logic on the rising edge of the clock.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_FF is
    Port (
        CLK : in STD_LOGIC;
        S   : in STD_LOGIC;
        R   : in STD_LOGIC;
        Q   : out STD_LOGIC
    );
end SR_FF;

architecture Behavioral of SR_FF is
    signal Q_int : STD_LOGIC := '0';
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            if S = '1' and R = '0' then
                Q_int <= '1';
            elsif R = '1' and S = '0' then
                Q_int <= '0';
            elsif S = '0' and R = '0' then
                Q_int <= Q_int; -- hold state
            else
                Q_int <= 'X'; -- invalid state when S=R=1
            end if;
        end if;
    end process;

    Q <= Q_int;
end Behavioral;

Output

No direct console output; Q changes according to S, R, and CLK inputs in simulation.

Common Pitfalls

Common mistakes when coding an SR flip flop in VHDL include:

• Not handling the invalid condition when both S and R are '1', which leads to an undefined output.
• Forgetting to use rising_edge(CLK) to trigger state changes only on clock edges.
• Assigning output Q directly inside the process without a signal to hold state, which can cause simulation mismatches.

vhdl

process(CLK)
begin
    if rising_edge(CLK) then
        if S = '1' and R = '1' then
            Q <= '0'; -- wrong: no invalid state handling
        elsif S = '1' then
            Q <= '1';
        elsif R = '1' then
            Q <= '0';
        end if;
    end if;
end process;

-- Correct approach:
process(CLK)
begin
    if rising_edge(CLK) then
        if S = '1' and R = '1' then
            Q <= 'X'; -- indicate invalid state
        elsif S = '1' then
            Q <= '1';
        elsif R = '1' then
            Q <= '0';
        end if;
    end if;
end process;

Quick Reference

Signal	Description
S	Set input, sets Q to '1' when active
R	Reset input, resets Q to '0' when active
CLK	Clock input, triggers flip flop on rising edge
Q	Output, holds the current state
S=R=1	Invalid state, output undefined ('X')

Key Takeaways

Use a process triggered by rising_edge(CLK) to model SR flip flop behavior.

Set Q to '1' when S=1 and R=0; reset Q to '0' when R=1 and S=0.

Handle the invalid condition when both S and R are '1' to avoid undefined output.

Hold the output state when both S and R are '0'.

Use an internal signal to store state before assigning to output port.