VHDL Code for BCD Adder: Syntax and Example

A BCD adder in VHDL adds two Binary-Coded Decimal digits and outputs the sum and carry. It uses a 4-bit adder with correction logic to adjust sums greater than 9 by adding 6. The code includes input ports for two BCD digits and a carry-in, and outputs the BCD sum and carry-out.

Syntax

The BCD adder entity defines inputs for two 4-bit BCD digits and a carry-in, and outputs a 4-bit sum and carry-out. The architecture uses a 4-bit binary adder and adds correction logic to adjust sums above 9 by adding 6 (0110 in binary).

• entity: declares inputs and outputs
• architecture: describes the logic
• signal: internal wires for sum and carry
• process: performs addition and correction

vhdl

entity bcd_adder is
    Port (
        A : in std_logic_vector(3 downto 0); -- First BCD digit
        B : in std_logic_vector(3 downto 0); -- Second BCD digit
        Cin : in std_logic;                   -- Carry input
        Sum : out std_logic_vector(3 downto 0); -- BCD sum output
        Cout : out std_logic                   -- Carry output
    );
end bcd_adder;

architecture Behavioral of bcd_adder is
    signal temp_sum : std_logic_vector(4 downto 0); -- 5 bits to hold sum + carry
    signal corrected_sum : std_logic_vector(4 downto 0);
begin
    process(A, B, Cin)
    begin
        temp_sum <= ('0' & A) + ('0' & B) + ("0000" & Cin);
        if (temp_sum > "01001") then  -- if sum > 9
            corrected_sum <= temp_sum + "00110"; -- add 6
        else
            corrected_sum <= temp_sum;
        end if;
        Sum <= corrected_sum(3 downto 0);
        Cout <= corrected_sum(4);
    end process;
end Behavioral;

Example

This example shows a complete VHDL BCD adder that adds two BCD digits and a carry-in. It outputs the corrected BCD sum and carry-out. The example demonstrates how to handle sums greater than 9 by adding 6 to correct the result.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity bcd_adder is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        Cin : in std_logic;
        Sum : out std_logic_vector(3 downto 0);
        Cout : out std_logic
    );
end bcd_adder;

architecture Behavioral of bcd_adder is
    signal temp_sum : unsigned(4 downto 0);
    signal corrected_sum : unsigned(4 downto 0);
begin
    process(A, B, Cin)
    begin
        temp_sum <= unsigned('0' & A) + unsigned('0' & B) + unsigned("0000" & Cin);
        if temp_sum > 9 then
            corrected_sum <= temp_sum + 6;
        else
            corrected_sum <= temp_sum;
        end if;
        Sum <= std_logic_vector(corrected_sum(3 downto 0));
        Cout <= corrected_sum(4);
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when writing a BCD adder in VHDL include:

• Not using 5 bits for the sum to hold carry properly.
• Forgetting to add 6 when the sum exceeds 9, causing invalid BCD output.
• Mixing std_logic_vector with arithmetic operations without conversion to unsigned or signed.
• Incorrectly handling the carry-in and carry-out bits.

Always convert vectors to unsigned before arithmetic and back to std_logic_vector for output.

vhdl

wrong approach:
process(A, B, Cin)
begin
    temp_sum <= A + B + Cin; -- Error: std_logic_vector addition without conversion
    if temp_sum > "1001" then
        temp_sum <= temp_sum + "0110";
    end if;
    Sum <= temp_sum(3 downto 0);
    Cout <= temp_sum(4);
end process;

correct approach:
process(A, B, Cin)
begin
    temp_sum <= unsigned('0' & A) + unsigned('0' & B) + unsigned("0000" & Cin);
    if temp_sum > 9 then
        temp_sum <= temp_sum + 6;
    end if;
    Sum <= std_logic_vector(temp_sum(3 downto 0));
    Cout <= temp_sum(4);
end process;

Quick Reference

Tips for writing a BCD adder in VHDL:

• Use 5-bit signals to hold sum and carry.
• Convert std_logic_vector to unsigned for arithmetic.
• Add 6 (0110) when sum > 9 to correct BCD output.
• Output the lower 4 bits as sum and the 5th bit as carry.
• Test with all BCD inputs (0 to 9) and carry-in 0 or 1.

Key Takeaways

Use 5-bit unsigned signals to hold the sum and carry during addition.

Add 6 to the sum when it exceeds 9 to correct the BCD output.

Always convert std_logic_vector to unsigned before arithmetic operations.

Output the lower 4 bits as the BCD sum and the highest bit as carry-out.

Test your BCD adder with all valid BCD inputs and carry-in values.