What Causes Latch Inference in VHDL and How to Avoid It

Latch inference in VHDL happens when a signal is assigned only in some branches of a conditional statement, causing the synthesis tool to create a memory element to hold the previous value. To avoid latch inference, ensure all signals are assigned in every possible path of your process or use clocked processes for sequential logic.

Syntax

Latch inference typically occurs inside a process block with conditional statements like if or case. The key syntax pattern is when a signal is assigned in some branches but not all, causing the tool to remember the last value.

• process: Defines a block of sequential code.
• if-elsif-else: Conditional branches.
• Signal assignments inside some but not all branches cause latch inference.

vhdl

process(a, b)
begin
  if a = '1' then
    q <= b;
  end if;
  -- No assignment to q when a /= '1' causes latch inference
end process;

Example

This example shows latch inference because q is assigned only when a = '1'. When a is not '1', q keeps its old value, so a latch is inferred.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity latch_example is
  port(
    a : in std_logic;
    b : in std_logic;
    q : out std_logic
  );
end latch_example;

architecture behavioral of latch_example is
begin
  process(a, b)
  begin
    if a = '1' then
      q <= b;
    end if;
    -- No else branch: q holds previous value, latch inferred
  end process;
end behavioral;

Common Pitfalls

Common mistakes that cause latch inference include:

• Not assigning a signal in every branch of an if or case statement.
• Using combinational processes without covering all input conditions.
• Forgetting an else branch or default assignment.

To fix this, always assign signals in all branches or use clocked processes for sequential logic.

vhdl

process(a, b)
begin
  if a = '1' then
    q <= b;  -- Assigned only here
  else
    q <= '0';  -- Assign in else to avoid latch
  end if;
end process;

Quick Reference

Cause	Effect	How to Fix
Signal assigned only in some branches	Latch inferred to hold value	Assign signal in all branches
No default or else branch in combinational process	Latch inferred	Add else or default assignment
Using combinational process for sequential logic	Unexpected latch or flip-flop	Use clocked process with rising_edge
Partial assignments inside case statements	Latch inferred	Cover all cases or add default

Key Takeaways

Latch inference occurs when signals are not assigned in every conditional path inside a process.

Always assign signals in all branches of if or case statements to avoid unintended latches.

Use clocked processes with rising_edge for sequential logic to prevent latch inference.

Missing else or default assignments in combinational logic often cause latch inference.

Review your VHDL code for complete signal assignments to ensure proper hardware synthesis.