How to Write Architecture in VHDL: Syntax and Example

In VHDL, an architecture describes the internal behavior or structure of an entity. You write it using the syntax architecture <name> of <entity> is ... begin ... end <name>; to define signals, components, and logic inside the design.

Syntax

The architecture block defines how an entity works internally. It starts with the keyword architecture, followed by a name, the keyword of, and the entity name it belongs to. Inside, you can declare signals and components before the begin keyword, then write the actual logic or structure. It ends with end and the architecture name.

• architecture <name> of <entity>: Declares the architecture and links it to an entity.
• is: Starts the declaration section for signals and components.
• begin: Starts the implementation section with processes or concurrent statements.
• end <name>;: Ends the architecture block.

vhdl

architecture Behavioral of MyEntity is
    -- signal declarations here
begin
    -- concurrent statements or processes here
end Behavioral;

Example

This example shows a simple architecture for an entity named MyEntity that implements a 2-input AND gate using concurrent signal assignment.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MyEntity is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end MyEntity;

architecture Behavioral of MyEntity is
begin
    Y <= A and B;  -- concurrent assignment implementing AND gate
end Behavioral;

Common Pitfalls

Common mistakes when writing architecture in VHDL include:

• Not matching the architecture name after end with the one after architecture.
• Forgetting to link the architecture to an existing entity.
• Placing signal declarations after the begin keyword instead of before.
• Using sequential statements outside of a process block.

vhdl

architecture Behavioral of MyEntity is
    signal temp : std_logic;
begin
    -- Wrong: signal declared after begin
    -- signal wrong_signal : std_logic;

    process(A, B)
    begin
        temp <= A and B;
        Y <= temp;
    end process;
end Behavioral;

Quick Reference

Part	Description
architecture <name> of <entity>	Declares the architecture and links it to an entity
is	Starts the declaration section for signals and components
begin	Starts the implementation section with logic or processes
end <name>;	Ends the architecture block, must match the architecture name

Key Takeaways

An architecture defines the internal behavior or structure of an entity in VHDL.

Always declare signals and components before the begin keyword inside architecture.

Match the architecture name after end with the one declared at the start.

Use concurrent statements outside processes and sequential statements inside processes.

Link the architecture to an existing entity using the syntax architecture of .