VHDL Code for Array Multiplier: Syntax and Example

An array multiplier in VHDL multiplies two binary numbers using an array of adders and AND gates. The code defines inputs as vectors, generates partial products, and sums them using a structured approach with for loops and signals.

Syntax

The array multiplier uses std_logic_vector inputs for the numbers to multiply. Partial products are generated by ANDing bits, then summed using adders arranged in an array pattern. The main parts include input declarations, signal declarations for partial products, and nested loops to create and sum these products.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity array_multiplier is
    generic (N : integer := 4);
    Port (
        A : in std_logic_vector(N-1 downto 0);
        B : in std_logic_vector(N-1 downto 0);
        P : out std_logic_vector(2*N-1 downto 0)
    );
end array_multiplier;

architecture Behavioral of array_multiplier is
    -- Signals for partial products and sums
begin
    -- Generate partial products and sum them
end Behavioral;

Example

This example shows a 4-bit array multiplier that multiplies two 4-bit inputs and outputs an 8-bit product. It uses nested loops to generate partial products and sums them using carry-save addition logic.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity array_multiplier is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        P : out std_logic_vector(7 downto 0)
    );
end array_multiplier;

architecture Behavioral of array_multiplier is
begin
    process(A, B)
        variable temp : unsigned(7 downto 0) := (others => '0');
    begin
        temp := (others => '0');
        for i in 0 to 3 loop
            for j in 0 to 3 loop
                if B(j) = '1' then
                    temp(i+j) := temp(i+j) or A(i);
                end if;
            end loop;
        end loop;
        P <= std_logic_vector(temp);
    end process;
end Behavioral;

Common Pitfalls

Common mistakes include mismatching vector sizes for inputs and outputs, not properly handling carry bits in addition, and incorrect indexing in loops causing wrong partial product placement. Forgetting to convert between std_logic_vector and unsigned types can cause synthesis errors.

Always ensure the output width is double the input width to hold the full product. Use proper type conversions when performing arithmetic.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Wrong: output width too small
entity wrong_multiplier is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        P : out std_logic_vector(5 downto 0) -- should be 7 downto 0
    );
end wrong_multiplier;

-- Right: output width correct
entity correct_multiplier is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        P : out std_logic_vector(7 downto 0)
    );
end correct_multiplier;

Quick Reference

• Input vectors size: N bits
• Output vector size: 2*N bits
• Partial products generated by bitwise AND of inputs
• Sum partial products using adders arranged in array
• Use unsigned type for arithmetic operations
• Convert between std_logic_vector and unsigned as needed

Key Takeaways

An array multiplier multiplies two binary vectors by generating and summing partial products.

Use input vectors of size N and output vector of size 2*N to hold the full product.

Handle carries carefully when summing partial products to avoid errors.

Convert between std_logic_vector and unsigned types for arithmetic operations.

Check vector indexing and sizes to prevent synthesis and runtime issues.