How to Use TextIO in VHDL for File Input and Output

In VHDL, TextIO is used to read and write text files by including the ieee.std_logic_textio or std.textio libraries. You open files with file variables, then use procedures like readline and writeline to process lines of text in your simulation.

Syntax

To use TextIO in VHDL, you first include the library and package. Then declare a file variable for input or output. Use readline to read a line from the file into a line variable, and writeline to write a line to the file. You can read or write data types like string or integer using provided procedures.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity textio_example is
end entity;

architecture behavior of textio_example is
  file input_file  : text open read_mode is "input.txt";
  file output_file : text open write_mode is "output.txt";
  variable line_buffer : line;
  variable data_str    : string(1 to 100);
begin
  process
  begin
    readline(input_file, line_buffer); -- read one line
    read(line_buffer, data_str);      -- extract string from line
    writeline(output_file, line_buffer); -- write line to output
    wait;
  end process;
end architecture;

Example

This example reads lines from a text file named input.txt and writes them to output.txt. It shows how to open files, read lines, and write lines using TextIO.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity textio_demo is
end entity;

architecture sim of textio_demo is
  file input_file  : text open read_mode is "input.txt";
  file output_file : text open write_mode is "output.txt";
  variable line_buffer : line;
  variable read_str    : string(1 to 80);
begin
  process
  begin
    while not endfile(input_file) loop
      readline(input_file, line_buffer);
      read(line_buffer, read_str);
      writeline(output_file, line_buffer);
    end loop;
    wait;
  end process;
end architecture;

Common Pitfalls

• Forgetting to include std.textio or ieee.std_logic_textio causes compilation errors.
• Not opening files with the correct mode (read_mode or write_mode) leads to runtime errors.
• Using read or write incorrectly on the line variable can cause data extraction or writing issues.
• Not checking endfile before reading can cause simulation to fail.

Wrong way: Reading without checking endfile or missing library imports.

Right way: Always include std.textio, open files properly, and check endfile before reading.

vhdl

library ieee;
use ieee.std_logic_1164.all;
-- Missing: use std.textio.all;

entity wrong_textio is
end entity;

architecture wrong of wrong_textio is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
begin
  process
  begin
    -- Missing endfile check
    readline(input_file, line_buffer);
    wait;
  end process;
end architecture;

Quick Reference

• library ieee; and use std.textio.all; to include TextIO.
• Declare files with file myfile : text open read_mode is "filename.txt";
• Use readline(file, line_var); to read a line.
• Use read(line_var, variable); to extract data from the line.
• Use writeline(file, line_var); to write a line.
• Check endfile(file) before reading to avoid errors.

Key Takeaways

Always include the std.textio package to use TextIO features in VHDL.

Open files with the correct mode (read_mode or write_mode) before accessing them.

Use readline and writeline to handle lines of text, and read/write to extract or insert data.

Check endfile before reading to prevent runtime errors.

TextIO is mainly for simulation and testbench file handling, not synthesis.