VHDL Code for Hamming Code Encoder: Syntax and Example

A Hamming code encoder in VHDL generates parity bits for error detection and correction by combining input data bits using XOR operations. The encoder outputs a codeword with data and parity bits, typically implemented as a combinational circuit using signal assignments and process blocks.

Syntax

The basic syntax for a Hamming code encoder in VHDL includes defining an entity with input data bits and output codeword bits. The architecture implements the parity bit calculations using XOR operations on the input bits. Signals or variables hold intermediate parity results, and the final codeword is assigned by combining data and parity bits.

Key parts:

• entity: declares inputs and outputs
• architecture: contains the logic for parity calculation
• signal: stores intermediate parity bits
• process or concurrent assignments: perform XOR operations

vhdl

entity HammingEncoder is
    Port (
        data_in : in std_logic_vector(3 downto 0); -- 4 data bits
        code_out : out std_logic_vector(6 downto 0) -- 7 bits output (4 data + 3 parity)
    );
end HammingEncoder;

architecture Behavioral of HammingEncoder is
    signal p1, p2, p3 : std_logic;
begin
    -- Parity bit calculations
    p1 <= data_in(0) xor data_in(1) xor data_in(3);
    p2 <= data_in(0) xor data_in(2) xor data_in(3);
    p3 <= data_in(1) xor data_in(2) xor data_in(3);

    -- Assign codeword: p1 p2 data_in(0) p3 data_in(1) data_in(2) data_in(3)
    code_out <= p1 & p2 & data_in(0) & p3 & data_in(1) & data_in(2) & data_in(3);
end Behavioral;

Example

This example shows a simple Hamming (7,4) encoder in VHDL. It takes 4 data bits and outputs 7 bits including 3 parity bits. The parity bits are calculated using XOR of specific data bits to detect and correct single-bit errors.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HammingEncoder is
    Port (
        data_in : in std_logic_vector(3 downto 0); -- 4 data bits
        code_out : out std_logic_vector(6 downto 0) -- 7 bits output
    );
end HammingEncoder;

architecture Behavioral of HammingEncoder is
    signal p1, p2, p3 : std_logic;
begin
    -- Calculate parity bits
    p1 <= data_in(0) xor data_in(1) xor data_in(3);
    p2 <= data_in(0) xor data_in(2) xor data_in(3);
    p3 <= data_in(1) xor data_in(2) xor data_in(3);

    -- Construct the 7-bit codeword
    code_out <= p1 & p2 & data_in(0) & p3 & data_in(1) & data_in(2) & data_in(3);
end Behavioral;

Common Pitfalls

Common mistakes when writing a Hamming code encoder in VHDL include:

• Incorrect parity bit positions in the output codeword, which breaks error detection.
• Using wrong XOR combinations for parity bits, causing wrong parity calculation.
• Mixing up bit order (MSB vs LSB) in input or output vectors.
• Forgetting to include all required data bits in parity calculations.

Always double-check the parity bit formulas and the final codeword bit order.

vhdl

/* Wrong parity calculation example */
-- p1 <= data_in(0) xor data_in(2) xor data_in(3); -- Incorrect
-- Correct:
-- p1 <= data_in(0) xor data_in(1) xor data_in(3);

Quick Reference

Hamming (7,4) code uses 4 data bits and 3 parity bits. Parity bits are placed at positions 1, 2, and 4 (counting from 1). The parity bits cover specific data bits as follows:

Parity Bit	Covers Data Bits (positions)
p1 (bit 1)	data_in(0), data_in(1), data_in(3)
p2 (bit 2)	data_in(0), data_in(2), data_in(3)
p3 (bit 4)	data_in(1), data_in(2), data_in(3)

Key Takeaways

Use XOR operations on specific data bits to calculate parity bits for Hamming encoding.

Place parity bits at positions 1, 2, and 4 in the 7-bit output codeword.

Verify parity bit formulas carefully to ensure correct error detection and correction.

Keep consistent bit ordering between input data and output codeword.

Test your encoder with known inputs to confirm correct parity and output.