How to Apply Stimulus in VHDL Testbench: Simple Guide

To apply stimulus in a VHDL testbench, you create a process that assigns values to input signals over time using wait statements or clock cycles. This process simulates input changes to test your design's response within the testbench environment.

Syntax

In VHDL testbenches, stimulus is applied inside a process block where input signals are assigned values sequentially. You use wait for or wait until statements to control timing between stimulus changes.

Key parts:

• process: Defines a block to apply stimulus sequentially.
• signal_name <= value;: Assigns a value to an input signal.
• wait for time;: Pauses the process for a specified time.

vhdl

process
begin
    signal_name <= '0';
    wait for 10 ns;
    signal_name <= '1';
    wait for 10 ns;
    -- Repeat as needed
    wait;
end process;

Example

This example shows a simple testbench applying stimulus to a 1-bit input signal input_signal. It changes the signal from '0' to '1' every 10 nanoseconds to test a device under test (DUT).

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity tb_stimulus is
end tb_stimulus;

architecture behavior of tb_stimulus is
    signal input_signal : std_logic := '0';
    signal output_signal : std_logic;

    -- DUT component declaration
    component dut is
        port(
            input_sig : in std_logic;
            output_sig : out std_logic
        );
    end component;

begin
    -- Instantiate DUT
    uut: dut port map(
        input_sig => input_signal,
        output_sig => output_signal
    );

    -- Stimulus process
    stim_proc: process
    begin
        input_signal <= '0';
        wait for 10 ns;
        input_signal <= '1';
        wait for 10 ns;
        input_signal <= '0';
        wait for 10 ns;
        input_signal <= '1';
        wait for 10 ns;
        wait; -- stop process
    end process;
end behavior;

Common Pitfalls

Common mistakes when applying stimulus in VHDL testbenches include:

• Not using wait statements, causing all assignments to happen instantly.
• Forgetting to initialize signals before stimulus starts.
• Using wait; too early, which stops the process before all stimulus is applied.
• Mixing signal assignments with variable assignments incorrectly inside the process.

Correct timing control and signal initialization are essential for meaningful simulation results.

vhdl

process
begin
    -- Wrong: no wait, all assignments happen instantly
    signal_name <= '0';
    signal_name <= '1';
    wait;
end process;

process
begin
    -- Right: wait between assignments
    signal_name <= '0';
    wait for 10 ns;
    signal_name <= '1';
    wait for 10 ns;
    wait;
end process;

Quick Reference

Tips for applying stimulus in VHDL testbenches:

• Use a process block to apply stimulus sequentially.
• Control timing with wait for or wait until.
• Initialize signals before starting stimulus.
• Use wait; at the end to stop the process.
• Apply stimulus changes clearly and with enough delay for the DUT to respond.

Key Takeaways

Apply stimulus in a VHDL testbench using a process with signal assignments and wait statements.

Always include timing control with wait statements to simulate real input changes.

Initialize input signals before applying stimulus to avoid unknown states.

Use wait at the end of the process to prevent it from running indefinitely.

Avoid assigning multiple values to the same signal without waits between them.