VHDL Code for Bus Arbiter: Syntax and Example

A bus arbiter in VHDL controls access to a shared bus by granting one request at a time using priority logic. The basic code includes input request signals, an output grant signal, and a process that assigns grants based on requests. This ensures orderly communication between multiple devices sharing the bus.

Syntax

The bus arbiter uses input signals representing requests from devices and outputs a grant signal to allow one device to use the bus at a time. The main parts are:

• Inputs: Request signals from devices (e.g., req1, req2).
• Output: Grant signals (e.g., grant1, grant2) indicating which device can use the bus.
• Process block: Contains the logic to decide which request to grant based on priority.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Bus_Arbiter is
    Port (
        req1  : in  STD_LOGIC;
        req2  : in  STD_LOGIC;
        grant1: out STD_LOGIC;
        grant2: out STD_LOGIC
    );
end Bus_Arbiter;

architecture Behavioral of Bus_Arbiter is
begin
    process(req1, req2)
    begin
        if req1 = '1' then
            grant1 <= '1';
            grant2 <= '0';
        elsif req2 = '1' then
            grant1 <= '0';
            grant2 <= '1';
        else
            grant1 <= '0';
            grant2 <= '0';
        end if;
    end process;
end Behavioral;

Example

This example shows a simple 2-device bus arbiter where req1 has higher priority than req2. When both request, only grant1 is active. If no requests, no grants are given.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Bus_Arbiter is
    Port (
        req1  : in  STD_LOGIC;
        req2  : in  STD_LOGIC;
        grant1: out STD_LOGIC;
        grant2: out STD_LOGIC
    );
end Bus_Arbiter;

architecture Behavioral of Bus_Arbiter is
begin
    process(req1, req2)
    begin
        if req1 = '1' then
            grant1 <= '1';
            grant2 <= '0';
        elsif req2 = '1' then
            grant1 <= '0';
            grant2 <= '1';
        else
            grant1 <= '0';
            grant2 <= '0';
        end if;
    end process;
end Behavioral;

-- Testbench to simulate the arbiter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_Bus_Arbiter is
end tb_Bus_Arbiter;

architecture Behavioral of tb_Bus_Arbiter is
    signal req1, req2 : STD_LOGIC := '0';
    signal grant1, grant2 : STD_LOGIC;
begin
    uut: entity work.Bus_Arbiter
        port map(
            req1 => req1,
            req2 => req2,
            grant1 => grant1,
            grant2 => grant2
        );

    process
    begin
        -- No requests
        req1 <= '0'; req2 <= '0';
        wait for 10 ns;

        -- Request from device 2 only
        req1 <= '0'; req2 <= '1';
        wait for 10 ns;

        -- Request from device 1 only
        req1 <= '1'; req2 <= '0';
        wait for 10 ns;

        -- Both request, device 1 has priority
        req1 <= '1'; req2 <= '1';
        wait for 10 ns;

        wait;
    end process;
end Behavioral;

Output

Time(ns) | req1 | req2 | grant1 | grant2
---------------------------------------
0        | 0    | 0    | 0      | 0
10       | 0    | 1    | 0      | 1
20       | 1    | 0    | 1      | 0
30       | 1    | 1    | 1      | 0

Common Pitfalls

Common mistakes when writing a bus arbiter in VHDL include:

• Not handling the case when no requests are active, which can leave grant signals undefined.
• Assigning multiple grants at the same time, causing bus conflicts.
• Forgetting to include all request signals in the sensitivity list of the process, leading to simulation mismatches.
• Using blocking assignments (:=) instead of signal assignments (<=) inside processes.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Wrong: grants assigned without else, can cause multiple grants
architecture Wrong of Bus_Arbiter is
begin
    process(req1, req2)
    begin
        if req1 = '1' then
            grant1 <= '1';
        else
            grant1 <= '0';
        end if;
        if req2 = '1' then
            grant2 <= '1';
        else
            grant2 <= '0';
        end if;
    end process;
end Wrong;

-- Right: use if-elsif-else to assign only one grant
architecture Right of Bus_Arbiter is
begin
    process(req1, req2)
    begin
        if req1 = '1' then
            grant1 <= '1';
            grant2 <= '0';
        elsif req2 = '1' then
            grant1 <= '0';
            grant2 <= '1';
        else
            grant1 <= '0';
            grant2 <= '0';
        end if;
    end process;
end Right;

Quick Reference

Tips for writing a bus arbiter in VHDL:

• Use if-elsif-else structure to ensure only one grant is active.
• Include all request signals in the process sensitivity list.
• Initialize grant signals to '0' when no requests are active.
• Test with a simple testbench to verify priority and grant logic.

Key Takeaways

A bus arbiter grants access to one requester at a time using priority logic in VHDL.

Use if-elsif-else statements to avoid multiple grants and ensure clear priority.

Always include all request signals in the process sensitivity list for correct simulation.

Initialize grant outputs to '0' when no requests are active to avoid undefined states.

Test your arbiter with a simple testbench to verify correct grant behavior.