Concatenation Operator in VHDL: What It Is and How to Use

In VHDL, the & symbol is the concatenation operator used to join two or more bit vectors or signals into a single longer vector. It works like connecting pieces of a chain to form a bigger chain by placing one vector right after another.

How It Works

The concatenation operator in VHDL is represented by the & symbol. It joins two or more vectors or signals end-to-end to create a longer vector. Imagine you have two strips of colored tape, one red and one blue. Using concatenation is like sticking the blue tape right after the red tape to make one longer strip.

In VHDL, this is useful because signals often represent groups of bits, and sometimes you need to combine smaller groups into a bigger one. The operator simply places the bits of the second vector immediately after the bits of the first vector, preserving their order.

Example

This example shows how to concatenate two 4-bit vectors into one 8-bit vector.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity concat_example is
    port(
        a : in std_logic_vector(3 downto 0);
        b : in std_logic_vector(3 downto 0);
        c : out std_logic_vector(7 downto 0)
    );
end concat_example;

architecture behavior of concat_example is
begin
    c <= a & b;  -- Concatenate a and b
end behavior;

When to Use

Use the concatenation operator when you need to combine multiple smaller signals or bit vectors into a larger one. This is common in hardware design when assembling buses, creating wider data paths, or packaging control signals together.

For example, if you have two 4-bit inputs representing parts of an address, concatenation lets you form the full 8-bit address easily. It also helps when you want to add padding bits or combine flags with data bits in a single vector.

Key Points

• The concatenation operator is & in VHDL.
• It joins vectors end-to-end to form a longer vector.
• Order matters: the left vector bits come first, then the right.
• Useful for building wider buses or combining signals.

Key Takeaways

The concatenation operator & joins vectors end-to-end in VHDL.

It helps create wider signals by combining smaller bit vectors.

Order of vectors in concatenation affects the final bit arrangement.

Commonly used to build buses and assemble complex signals.