How to Read File in VHDL Testbench: Syntax and Example

In a VHDL testbench, you can read a file using the textio package by declaring the file with file keyword, then reading lines with readline and extracting data using read. This allows you to simulate input data from external files during testbench execution.

Syntax

To read a file in VHDL testbench, use the textio package. The main steps are:

• Declare a file variable for the input file.
• Use file_open to open the file in read mode (optional if declared with open read_mode).
• Use readline to read each line into a line variable.
• Use read to extract data from the line into variables.
• Close the file when done (optional, usually automatic at simulation end).

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb is
end entity;

architecture behavior of tb is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
  variable data_int : integer;
begin
  process
  begin
    while not endfile(input_file) loop
      readline(input_file, line_buffer);
      read(line_buffer, data_int);
      -- Use data_int as needed
    end loop;
    wait;
  end process;
end architecture;

Example

This example shows a simple VHDL testbench reading integers from a file named input.txt and printing them to the console using report. It demonstrates opening the file, reading lines, extracting integers, and handling end of file.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb is
end entity;

architecture behavior of tb is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
  variable data_int : integer;
begin
  process
  begin
    while not endfile(input_file) loop
      readline(input_file, line_buffer);
      read(line_buffer, data_int);
      report "Read integer: " & integer'image(data_int);
    end loop;
    wait;
  end process;
end architecture;

Output

Note: Read integer: 10
Note: Read integer: 20
Note: Read integer: 30

Common Pitfalls

• Forgetting to open the file in read_mode causes runtime errors.
• Not checking endfile before reading can cause infinite loops or errors.
• Incorrectly reading data types from the line leads to runtime exceptions.
• Not using variable for line and data variables inside the process causes compilation errors.

Always ensure the file path is correct relative to the simulation working directory.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity tb is
end entity;

architecture wrong_way of tb is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
  variable data_int : integer;
begin
  process
  begin
    -- Wrong: missing endfile check
    readline(input_file, line_buffer);
    read(line_buffer, data_int);
    report "Read integer: " & integer'image(data_int);
    wait;
  end process;
end architecture;

architecture right_way of tb is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
  variable data_int : integer;
begin
  process
  begin
    while not endfile(input_file) loop
      readline(input_file, line_buffer);
      read(line_buffer, data_int);
      report "Read integer: " & integer'image(data_int);
    end loop;
    wait;
  end process;
end architecture;

Quick Reference

Step	Description
Declare file variable	file input_file : text open read_mode is "filename.txt";
Open file	Automatically opened by declaration with mode
Check end of file	while not endfile(input_file) loop
Read line	readline(input_file, line_buffer);
Extract data	read(line_buffer, variable);
Close file	Automatically closed at simulation end

Key Takeaways

Use the std.textio package to read files in VHDL testbenches.

Always check endfile before reading lines to avoid errors.

Use variables for line buffers and data inside processes.

Open files in read_mode and ensure the file path is correct.

Use readline and read to extract data from each line.