VHDL Code for Stopwatch: Syntax, Example, and Tips

A stopwatch in VHDL can be created using a clock-driven process that counts clock pulses to measure time intervals. The design typically includes a counter, start/stop control signals, and reset functionality implemented inside a process block sensitive to the clock and reset signals.

Syntax

The basic syntax for a stopwatch in VHDL involves defining an entity with input signals like clk (clock), reset, and control signals such as start and stop. Inside the architecture, a process block uses these signals to control a counter that increments on each clock cycle when running.

• entity: Defines inputs and outputs.
• architecture: Contains the logic.
• process: Runs on clock and reset events.
• counter: Counts clock ticks to measure time.
• start/stop: Control counting.
• reset: Resets the counter to zero.

vhdl

entity Stopwatch is
    Port (
        clk    : in  std_logic;
        reset  : in  std_logic;
        start  : in  std_logic;
        stop   : in  std_logic;
        time_count : out unsigned(15 downto 0)
    );
end Stopwatch;

architecture Behavioral of Stopwatch is
    signal counter : unsigned(15 downto 0) := (others => '0');
    signal running : std_logic := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
            running <= '0';
        elsif rising_edge(clk) then
            if start = '1' then
                running <= '1';
            elsif stop = '1' then
                running <= '0';
            end if;

            if running = '1' then
                counter <= counter + 1;
            end if;
        end if;
    end process;

    time_count <= counter;
end Behavioral;

Example

This example shows a simple stopwatch that counts clock cycles when started and stops counting when stopped. The time_count output shows the current count value.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Stopwatch is
    Port (
        clk    : in  std_logic;
        reset  : in  std_logic;
        start  : in  std_logic;
        stop   : in  std_logic;
        time_count : out unsigned(15 downto 0)
    );
end Stopwatch;

architecture Behavioral of Stopwatch is
    signal counter : unsigned(15 downto 0) := (others => '0');
    signal running : std_logic := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
            running <= '0';
        elsif rising_edge(clk) then
            if start = '1' then
                running <= '1';
            elsif stop = '1' then
                running <= '0';
            end if;

            if running = '1' then
                counter <= counter + 1;
            end if;
        end if;
    end process;

    time_count <= counter;
end Behavioral;

Output

When simulated, the counter increments by 1 on each rising clock edge while <code>start</code> is high and stops incrementing when <code>stop</code> is high. Reset sets the counter to zero.

Common Pitfalls

Common mistakes when writing a VHDL stopwatch include:

• Not handling the reset signal properly, causing the counter to not reset.
• Forgetting to check for rising clock edges, which can cause multiple increments per clock cycle.
• Not controlling the running state correctly, leading to continuous counting or no counting.
• Using signals instead of variables inside the process incorrectly, causing unexpected delays.

Always use rising_edge(clk) for clock detection and synchronous reset for reliable operation.

vhdl

Wrong way:
process(clk)
begin
    if clk = '1' then  -- Incorrect: level check, not edge
        counter <= counter + 1;
    end if;
end process;

Right way:
process(clk)
begin
    if rising_edge(clk) then
        counter <= counter + 1;
    end if;
end process;

Quick Reference

Tips for building a VHDL stopwatch:

• Use unsigned type for counters to easily add values.
• Control counting with a running signal set by start and stop inputs.
• Reset the counter synchronously or asynchronously for clean start.
• Use rising_edge(clk) to detect clock ticks.
• Output the counter value as the stopwatch time.

Key Takeaways

Use a clock-driven process with rising_edge detection to count time in VHDL.

Control counting with start and stop signals to manage stopwatch state.

Always reset the counter properly to ensure correct timing.

Use unsigned counters for easy arithmetic operations.

Avoid level-sensitive clock checks to prevent multiple increments per cycle.