VHDL Code for LFSR: Syntax, Example, and Common Pitfalls

A Linear Feedback Shift Register (LFSR) in VHDL is implemented using a shift register with feedback taps combined by XOR gates. Use a process triggered by clock edges to shift bits and update the register state with feedback. The feedback polynomial defines which bits to XOR for the new input bit.

Syntax

An LFSR in VHDL typically uses a signal to hold the register bits and a process triggered on the rising edge of the clock. Inside the process, the register shifts right, and the new leftmost bit is the XOR of selected bits (feedback taps). Reset logic initializes the register.

• signal lfsr_reg: holds the current bits of the LFSR.
• process(clk, reset): updates the register on clock edges or resets it.
• feedback calculation: XOR of specific bits based on the polynomial.

vhdl

process(clk, reset)
begin
  if reset = '1' then
    lfsr_reg <= (others => '1'); -- initial state
  elsif rising_edge(clk) then
    lfsr_reg <= lfsr_reg(lfsr_reg'length-2 downto 0) & feedback_bit;
  end if;
end process;

Example

This example shows a 4-bit LFSR with taps at bits 4 and 3 (polynomial x^4 + x^3 + 1). It shifts bits on each clock cycle and outputs the current LFSR value.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_4bit is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    q     : out std_logic_vector(3 downto 0)
  );
end entity;

architecture rtl of lfsr_4bit is
  signal lfsr_reg : std_logic_vector(3 downto 0) := "1111";
  signal feedback_bit : std_logic;
begin
  feedback_bit <= lfsr_reg(3) xor lfsr_reg(2); -- taps at bit 4 and 3

  process(clk, reset)
  begin
    if reset = '1' then
      lfsr_reg <= "1111"; -- initial state
    elsif rising_edge(clk) then
      lfsr_reg <= lfsr_reg(2 downto 0) & feedback_bit;
    end if;
  end process;

  q <= lfsr_reg;
end architecture;

Output

On each clock cycle, the output q cycles through a pseudo-random sequence of 4-bit values excluding all zeros.

Common Pitfalls

Common mistakes when coding LFSRs in VHDL include:

• Not initializing the register to a non-zero value, causing the LFSR to lock at zero.
• Incorrect feedback taps that do not produce maximal length sequences.
• Forgetting to use rising_edge(clk) for synchronous updates.
• Mixing bit order in the shift operation, causing unexpected sequences.

vhdl

-- Wrong: No reset initialization
process(clk)
begin
  if rising_edge(clk) then
    lfsr_reg <= lfsr_reg(2 downto 0) & feedback_bit;
  end if;
end process;

-- Right: With reset initialization
process(clk, reset)
begin
  if reset = '1' then
    lfsr_reg <= "1111";
  elsif rising_edge(clk) then
    lfsr_reg <= lfsr_reg(2 downto 0) & feedback_bit;
  end if;
end process;

Quick Reference

Remember these key points when writing an LFSR in VHDL:

• Initialize the register to a non-zero value on reset.
• Use XOR of correct taps for feedback bit.
• Shift bits correctly on each clock rising edge.
• Output the current register state as the LFSR value.

Key Takeaways

Always initialize the LFSR register to a non-zero value to avoid lock-up.

Use XOR of specific bits (taps) to generate the feedback bit for maximal sequences.

Update the LFSR synchronously on the rising edge of the clock.

Shift the register bits correctly to maintain the sequence order.

Verify the feedback polynomial to ensure the desired pseudo-random pattern.