What Constructs Are Not Synthesizable in VHDL: Key Limitations

In VHDL, constructs like file I/O operations, wait statements without sensitivity, and unconstrained loops or recursion are not synthesizable. Also, dynamic memory allocation and certain textio operations cannot be converted into hardware by synthesis tools.

Syntax

Here are some common VHDL constructs that are not synthesizable and their typical syntax:

• File I/O: file variable_name : text open read_mode "filename";
• Wait statement without sensitivity list: wait; or wait for time;
• Recursion: A function calling itself, e.g., function factorial(n: integer) return integer is begin if n = 0 then return 1; else return n * factorial(n-1); end if; end factorial;
• Dynamic loops: Loops where the number of iterations depends on a variable or input, e.g., for i in 0 to variable loop ... end loop;

vhdl

file myfile : text open read_mode is "input.txt";

process
begin
  wait;
end process;

function factorial(n: integer) return integer is
begin
  if n = 0 then
    return 1;
  else
    return n * factorial(n-1);
  end if;
end factorial;

process
  variable i: integer := 0;
  variable limit: integer := 10;
begin
  for i in 0 to limit loop
    -- loop body
  end loop;
end process;

Example

This example shows a process using a wait; statement without sensitivity list and a file read operation, both of which are not synthesizable.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity non_synth_example is
  port(
    clk : in std_logic;
    data_out : out std_logic_vector(7 downto 0)
  );
end entity;

architecture Behavioral of non_synth_example is
  file input_file : text open read_mode is "input.txt";
  variable line_buffer : line;
  variable data_byte : integer;
begin
  process
  begin
    -- Non-synthesizable wait statement
    wait;
  end process;

  process(clk)
  begin
    if rising_edge(clk) then
      if not endfile(input_file) then
        readline(input_file, line_buffer);
        read(line_buffer, data_byte);
        data_out <= std_logic_vector(to_unsigned(data_byte, 8));
      end if;
    end if;
  end process;
end Behavioral;

Common Pitfalls

Many beginners try to use wait; statements or file operations in synthesizable code, which synthesis tools cannot convert to hardware. Also, using loops with variable bounds or recursion causes synthesis errors because hardware requires fixed, static structures.

Incorrect example:

process
begin
  wait;
end process;

This process never ends and cannot be synthesized.

Correct approach:

process(clk)
begin
  if rising_edge(clk) then
    -- synchronous logic here
  end if;
end process;

Quick Reference

Non-Synthesizable VHDL Constructs	Reason
File I/O operations (textio)	Cannot map to hardware signals or registers
Wait statements without sensitivity	Infinite or uncontrolled wait not hardware-friendly
Recursion	Hardware requires fixed structure, recursion is dynamic
Loops with variable bounds	Hardware loops must have fixed iteration counts
Dynamic memory allocation	Hardware memory sizes must be fixed at compile time

Key Takeaways

Avoid using file I/O and textio operations in synthesizable VHDL code.

Do not use wait statements without sensitivity lists in hardware design.

Recursion and loops with variable bounds are not synthesizable.

Synthesis requires fixed, static hardware structures with known sizes.

Use clocked processes and static loops for synthesizable VHDL.