VHDL Code for Floating Point Addition: Syntax and Example

In VHDL, floating point addition is typically done using the IEEE floating point packages like ieee.float_pkg. You instantiate floating point signals and use the + operator directly for addition after including the proper libraries.

Syntax

To perform floating point addition in VHDL, you first include the IEEE floating point package. Then declare signals of floating point type and use the + operator to add them.

• library ieee; - imports IEEE standard libraries.
• use ieee.float_pkg.all; - imports floating point types and operators.
• signal a, b, result : float32; - declares 32-bit floating point signals.
• result <= a + b; - performs floating point addition.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;

entity fp_add is
  port(
    a, b : in float32;
    result : out float32
  );
end entity fp_add;

architecture rtl of fp_add is
begin
  result <= a + b;
end architecture rtl;

Example

This example shows a simple VHDL entity that adds two 32-bit floating point inputs and outputs the result. It uses the IEEE float_pkg package for floating point support.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;

entity fp_adder is
  port(
    a, b : in float32;
    sum : out float32
  );
end entity fp_adder;

architecture behavioral of fp_adder is
begin
  sum <= a + b;
end architecture behavioral;

Common Pitfalls

Common mistakes when doing floating point addition in VHDL include:

• Not including ieee.float_pkg which provides floating point types and operators.
• Using std_logic_vector instead of floating point types, which requires manual conversion and is error-prone.
• Ignoring the need for synthesis tools that support floating point operations.

Always ensure your synthesis tool supports the floating point package or use IP cores designed for floating point arithmetic.

vhdl

library ieee;
use ieee.std_logic_1164.all;
-- Missing float_pkg causes errors

entity wrong_fp_add is
  port(
    a, b : in std_logic_vector(31 downto 0);
    result : out std_logic_vector(31 downto 0)
  );
end entity wrong_fp_add;

architecture wrong_arch of wrong_fp_add is
begin
  -- This will not work for floating point addition directly
  result <= a + b; -- Error: '+' not defined for std_logic_vector
end architecture wrong_arch;

-- Correct way:
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;

entity correct_fp_add is
  port(
    a, b : in float32;
    result : out float32
  );
end entity correct_fp_add;

architecture correct_arch of correct_fp_add is
begin
  result <= a + b; -- Works correctly
end architecture correct_arch;

Quick Reference

Summary tips for floating point addition in VHDL:

• Always include ieee.float_pkg for floating point types and operators.
• Use float32 or float64 types for your signals.
• Use the + operator directly on floating point signals.
• Check your synthesis tool supports floating point operations or use IP cores.

Key Takeaways

Include ieee.float_pkg to use floating point types and operators in VHDL.

Declare signals with float32 or float64 types for floating point arithmetic.

Use the + operator directly on floating point signals for addition.

Ensure your synthesis tool supports floating point operations or use dedicated IP cores.

Avoid using std_logic_vector for floating point without proper conversion.