VHDL Code for Priority Encoder: Syntax and Example

A priority encoder in VHDL is a circuit that outputs the binary code of the highest priority active input. You write it using a process block that checks inputs in priority order and sets the output accordingly. The code uses if-elsif statements to detect the highest priority input.

Syntax

The basic syntax of a priority encoder in VHDL uses a process block triggered by input changes. Inside, if-elsif statements check each input in order of priority. The output is assigned the binary code of the highest priority input that is active.

• process: Defines a block that reacts to input changes.
• if-elsif: Checks inputs from highest to lowest priority.
• output assignment: Sets the output to the input's binary code.

vhdl

process(inputs) is
begin
  if inputs(3) = '1' then
    output <= "11";
  elsif inputs(2) = '1' then
    output <= "10";
  elsif inputs(1) = '1' then
    output <= "01";
  elsif inputs(0) = '1' then
    output <= "00";
  else
    output <= "00"; -- default output if no input is active
  end if;
end process;

Example

This example shows a 4-to-2 priority encoder in VHDL. It checks inputs from highest (input 3) to lowest (input 0) and outputs the binary code of the highest active input. If no inputs are active, the output is "00".

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PriorityEncoder4to2 is
  Port (
    inputs : in STD_LOGIC_VECTOR(3 downto 0);
    output : out STD_LOGIC_VECTOR(1 downto 0);
    valid : out STD_LOGIC
  );
end PriorityEncoder4to2;

architecture Behavioral of PriorityEncoder4to2 is
begin
  process(inputs) is
  begin
    valid <= '0';
    if inputs(3) = '1' then
      output <= "11";
      valid <= '1';
    elsif inputs(2) = '1' then
      output <= "10";
      valid <= '1';
    elsif inputs(1) = '1' then
      output <= "01";
      valid <= '1';
    elsif inputs(0) = '1' then
      output <= "00";
      valid <= '1';
    else
      output <= "00";
      valid <= '0';
    end if;
  end process;
end Behavioral;

Output

For inputs = "0101" (inputs 2 and 0 active), output = "10", valid = '1' (input 2 has higher priority).

Common Pitfalls

Common mistakes when writing a priority encoder in VHDL include:

• Not checking inputs in correct priority order, causing wrong output.
• Forgetting to set a valid signal to indicate if any input is active.
• Not providing a default output when no inputs are active.
• Using if statements without elsif, which can cause multiple outputs to be assigned.

vhdl

process(inputs) is
begin
  -- Wrong: checks inputs in wrong order
  if inputs(0) = '1' then
    output <= "00";
  elsif inputs(1) = '1' then
    output <= "01";
  elsif inputs(2) = '1' then
    output <= "10";
  elsif inputs(3) = '1' then
    output <= "11";
  else
    output <= "00";
  end if;
end process;

-- Right: checks inputs from highest to lowest priority
process(inputs) is
begin
  if inputs(3) = '1' then
    output <= "11";
  elsif inputs(2) = '1' then
    output <= "10";
  elsif inputs(1) = '1' then
    output <= "01";
  elsif inputs(0) = '1' then
    output <= "00";
  else
    output <= "00";
  end if;
end process;

Quick Reference

Tips for writing a priority encoder in VHDL:

• Always check inputs from highest to lowest priority using if-elsif.
• Use a valid signal to indicate if any input is active.
• Provide a default output for no active inputs.
• Use STD_LOGIC_VECTOR for inputs and outputs.
• Test with multiple inputs active to verify priority behavior.

Key Takeaways

Check inputs in descending priority order using if-elsif to ensure correct output.

Include a valid signal to indicate when an input is active.

Always provide a default output for the case when no inputs are active.

Use STD_LOGIC_VECTOR types for inputs and outputs for clarity.

Test your priority encoder with multiple active inputs to confirm priority logic.