VHDL Code for Edge Detector: Syntax and Example

An edge detector in VHDL detects changes in a signal by comparing its current and previous values using a process block with a clock. The typical code stores the previous signal state and outputs a pulse when a rising or falling edge is detected.

Syntax

An edge detector in VHDL uses a process triggered by a clock signal. Inside, it stores the previous value of the input signal in a register and compares it to the current value. When the input changes from 0 to 1 (rising edge) or 1 to 0 (falling edge), the output signal is set accordingly.

• clk: Clock signal to synchronize detection.
• signal_in: Input signal to monitor.
• signal_out: Output pulse indicating edge detection.
• prev_signal: Internal register holding previous input state.

vhdl

process(clk)
begin
  if rising_edge(clk) then
    signal_out <= '1' when (signal_in = '1' and prev_signal = '0') else '0';
    prev_signal <= signal_in;
  end if;
end process;

Example

This example shows a simple rising edge detector. It outputs '1' for one clock cycle when the input signal changes from '0' to '1'.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity edge_detector is
  Port (
    clk       : in  STD_LOGIC;
    signal_in : in  STD_LOGIC;
    signal_out: out STD_LOGIC
  );
end edge_detector;

architecture Behavioral of edge_detector is
  signal prev_signal : STD_LOGIC := '0';
begin
  process(clk)
  begin
    if rising_edge(clk) then
      signal_out <= '1' when (signal_in = '1' and prev_signal = '0') else '0';
      prev_signal <= signal_in;
    end if;
  end process;
end Behavioral;

Output

On each rising clock edge, signal_out is '1' for one cycle when signal_in rises from '0' to '1', otherwise '0'.

Common Pitfalls

Common mistakes include:

• Not using a clock to synchronize the detection, causing unreliable outputs.
• Updating the previous signal before output assignment, which can cause timing errors.
• Detecting edges without storing previous state, making edge detection impossible.

Always update the previous signal after generating the output inside the clocked process.

vhdl

process(clk)
begin
  if rising_edge(clk) then
    prev_signal <= signal_in;  -- Wrong: updating before output
    signal_out <= '1' when (signal_in = '1' and prev_signal = '0') else '0';
  end if;
end process;

-- Correct order:
process(clk)
begin
  if rising_edge(clk) then
    signal_out <= '1' when (signal_in = '1' and prev_signal = '0') else '0';
    prev_signal <= signal_in;
  end if;
end process;

Quick Reference

Term	Description
clk	Clock signal to synchronize edge detection
signal_in	Input signal to monitor for edges
signal_out	Output pulse indicating detected edge
prev_signal	Register holding previous input state
rising_edge(clk)	Detects clock rising edge for synchronous logic

Key Takeaways

Use a clocked process to reliably detect edges in VHDL.

Store the previous input value to compare with the current input.

Output a pulse when the input changes from '0' to '1' for rising edge detection.

Update the previous signal after setting the output inside the process.

Avoid combinational edge detection without a clock for stable results.