How to Create VCD Waveform in VHDL for Simulation

To create a VCD waveform in VHDL, you write a testbench that simulates your design and run it in a VHDL simulator with VCD output enabled. The simulator records signal changes during simulation and saves them in a .vcd file, which you can view with waveform viewers.

Syntax

VHDL itself does not have direct syntax to create VCD files; instead, you write a testbench to simulate your design and use your VHDL simulator's command or options to generate the VCD file.

Typical steps include:

• Write a testbench that instantiates your design and applies stimulus.
• Run the simulation with VCD dumping enabled (usually a command line option).
• The simulator creates a .vcd file recording signal changes.

Example command line options vary by simulator:

• ModelSim/QuestaSim: vsim -vcdfile waveform.vcd work.testbench
• GHDL: ghdl -r testbench --vcd=waveform.vcd

vhdl

entity testbench is
end testbench;

architecture behavior of testbench is
    -- Component declaration for the design under test (DUT)
    component my_design
        port(
            clk : in std_logic;
            rst : in std_logic;
            out_signal : out std_logic
        );
    end component;

    signal clk : std_logic := '0';
    signal rst : std_logic := '1';
    signal out_signal : std_logic;

begin
    -- Instantiate the DUT
    uut: my_design port map(clk => clk, rst => rst, out_signal => out_signal);

    -- Clock generation process
    clk_process : process
    begin
        clk <= '0';
        wait for 10 ns;
        clk <= '1';
        wait for 10 ns;
    end process;

    -- Stimulus process
    stim_proc: process
    begin
        rst <= '1';
        wait for 25 ns;
        rst <= '0';
        wait for 100 ns;
        wait;
    end process;
end behavior;

Example

This example shows a simple testbench for a clocked process and how to run it with GHDL to generate a VCD waveform file named waveform.vcd. You can open this file in any waveform viewer like GTKWave.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity my_design is
    port(
        clk : in std_logic;
        rst : in std_logic;
        out_signal : out std_logic
    );
end my_design;

architecture rtl of my_design is
    signal count : integer := 0;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= 0;
            out_signal <= '0';
        elsif rising_edge(clk) then
            count <= count + 1;
            if count mod 2 = 0 then
                out_signal <= '1';
            else
                out_signal <= '0';
            end if;
        end if;
    end process;
end rtl;

-- Testbench
entity testbench is
end testbench;

architecture behavior of testbench is
    signal clk : std_logic := '0';
    signal rst : std_logic := '1';
    signal out_signal : std_logic;
begin
    uut: entity work.my_design
        port map(clk => clk, rst => rst, out_signal => out_signal);

    clk_process : process
    begin
        while true loop
            clk <= '0';
            wait for 10 ns;
            clk <= '1';
            wait for 10 ns;
        end loop;
    end process;

    stim_proc: process
    begin
        rst <= '1';
        wait for 25 ns;
        rst <= '0';
        wait for 200 ns;
        wait;
    end process;
end behavior;

Output

Simulation runs and creates waveform.vcd file with signal changes for clk, rst, and out_signal.

Common Pitfalls

• Not enabling VCD output in the simulator: Writing a testbench alone does not create a VCD file; you must run the simulator with the correct option to dump VCD.
• Forgetting to include signals in the waveform: Some simulators require you to specify which signals to record.
• Incorrect testbench stimulus: Without proper clock and reset signals, the waveform will not show meaningful activity.
• Using incompatible simulator commands: Each simulator has its own way to enable VCD output; check your tool's documentation.

vhdl

/* Wrong: Running simulation without VCD option (ModelSim example) */
-- vsim work.testbench

/* Right: Running simulation with VCD option */
-- vsim -vcdfile waveform.vcd work.testbench

Quick Reference

Summary tips for creating VCD waveforms in VHDL:

• Write a testbench that drives your design signals.
• Use your simulator's command line option to enable VCD dumping.
• Run the simulation long enough to capture signal changes.
• Open the generated .vcd file in a waveform viewer like GTKWave.

Key Takeaways

VHDL testbenches simulate your design but VCD files are created by the simulator with specific options.

Always enable VCD dumping in your simulator command to generate waveform files.

Include clock and reset signals in your testbench to see meaningful waveforms.

Use waveform viewers like GTKWave to open and analyze the generated .vcd files.