VHDL Code for Traffic Light Controller: Syntax and Example

A traffic light controller in VHDL uses a finite state machine to cycle through light states with timers. The code defines states for red, green, and yellow lights and transitions between them using a clock signal and counters.

Syntax

A traffic light controller in VHDL typically uses a process block triggered by a clock and reset signal. Inside, a case statement handles different states like RED, GREEN, and YELLOW. Counters track how long each light stays on before switching.

• entity: Defines inputs (clock, reset) and outputs (lights).
• architecture: Contains the logic and state machine.
• type state_type: Enumerates traffic light states.
• signal state: Holds current state.
• process(clock, reset): Runs on clock edge or reset.
• case state is: Controls state transitions.

vhdl

entity TrafficLightController is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        red_light : out std_logic;
        yellow_light : out std_logic;
        green_light : out std_logic
    );
end TrafficLightController;

architecture Behavioral of TrafficLightController is
    type state_type is (RED, GREEN, YELLOW);
    signal state : state_type := RED;
    signal counter : integer := 0;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= RED;
            counter <= 0;
        elsif rising_edge(clk) then
            -- state machine logic here
        end if;
    end process;
end Behavioral;

Example

This example shows a simple traffic light controller cycling through red, green, and yellow lights with fixed durations using a clock and reset.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity TrafficLightController is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        red_light : out std_logic;
        yellow_light : out std_logic;
        green_light : out std_logic
    );
end TrafficLightController;

architecture Behavioral of TrafficLightController is
    type state_type is (RED, GREEN, YELLOW);
    signal state : state_type := RED;
    signal counter : integer range 0 to 9 := 0; -- counts clock cycles
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= RED;
            counter <= 0;
        elsif rising_edge(clk) then
            case state is
                when RED =>
                    red_light <= '1';
                    yellow_light <= '0';
                    green_light <= '0';
                    if counter = 4 then -- red for 5 cycles
                        state <= GREEN;
                        counter <= 0;
                    else
                        counter <= counter + 1;
                    end if;
                when GREEN =>
                    red_light <= '0';
                    yellow_light <= '0';
                    green_light <= '1';
                    if counter = 4 then -- green for 5 cycles
                        state <= YELLOW;
                        counter <= 0;
                    else
                        counter <= counter + 1;
                    end if;
                when YELLOW =>
                    red_light <= '0';
                    yellow_light <= '1';
                    green_light <= '0';
                    if counter = 1 then -- yellow for 2 cycles
                        state <= RED;
                        counter <= 0;
                    else
                        counter <= counter + 1;
                    end if;
            end case;
        end if;
    end process;
end Behavioral;

Output

The traffic light cycles: RED light ON for 5 clock cycles, then GREEN light ON for 5 clock cycles, then YELLOW light ON for 2 clock cycles, repeating continuously.

Common Pitfalls

Common mistakes include:

• Not resetting the counter when changing states, causing incorrect timing.
• Forgetting to assign all output signals in every state, which can cause latches or unknown outputs.
• Using blocking assignments instead of signal assignments, which is not valid in VHDL.
• Not handling the reset signal properly, leading to undefined initial states.

vhdl

Wrong way (missing counter reset):
process(clk, reset)
begin
    if reset = '1' then
        state <= RED;
        counter <= 0;
    elsif rising_edge(clk) then
        case state is
            when RED =>
                if counter = 4 then
                    state <= GREEN;
                    -- counter not reset here causes errors
                else
                    counter <= counter + 1;
                end if;
            -- other states omitted
        end case;
    end if;
end process;

Right way (reset counter on state change):
process(clk, reset)
begin
    if reset = '1' then
        state <= RED;
        counter <= 0;
    elsif rising_edge(clk) then
        case state is
            when RED =>
                if counter = 4 then
                    state <= GREEN;
                    counter <= 0; -- reset counter
                else
                    counter <= counter + 1;
                end if;
            -- other states omitted
        end case;
    end if;
end process;

Quick Reference

Remember these key points for a VHDL traffic light controller:

• Use an enum type for states.
• Use a process triggered by clock and reset.
• Use a case statement for state transitions.
• Use counters to time each light duration.
• Reset counters on state changes.
• Assign all outputs in every state to avoid latches.

Key Takeaways

Use a finite state machine with states RED, GREEN, and YELLOW to control the traffic lights.

Implement timing with counters that reset on each state transition.

Always assign outputs in every state to avoid unintended latches.

Handle the reset signal to initialize the controller safely.

Test your design with a clock to verify correct light sequencing.