How to Use Array in VHDL: Syntax and Examples

In VHDL, you use array by defining a new type with type and then declaring signals or variables of that type. Arrays group multiple elements of the same type, like bits or integers, allowing you to handle collections easily.

Syntax

To use an array in VHDL, first define an array type with type. Then declare signals or variables using this type. The syntax includes specifying the element type and the range of indices.

• type: Defines the array type.
• element_type: The data type of each element (e.g., bit, integer).
• range: The index range (e.g., 0 to 7 or 7 downto 0).

vhdl

type my_array is array (0 to 7) of bit;
signal data : my_array;

Example

This example shows how to declare an array of 8 bits, assign values, and use it in a simple process that outputs the bits.

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity array_example is
    port(
        clk : in std_logic;
        out_bits : out std_logic_vector(7 downto 0)
    );
end entity;

architecture behavior of array_example is
    type bit_array is array (7 downto 0) of std_logic;
    signal data : bit_array := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            data <= (7 => '1', others => '0'); -- set MSB to '1'
        end if;
    end process;

    out_bits <= data;
end architecture;

Common Pitfalls

Common mistakes when using arrays in VHDL include:

• Not defining the array type before using it.
• Mixing index directions (e.g., using 0 to 7 but assigning with 7 downto 0).
• Assigning incompatible types (e.g., assigning std_logic_vector to a custom array without conversion).

Always ensure the array type matches the usage and index ranges are consistent.

vhdl

-- Wrong: Using array without type definition
signal data : array (0 to 7) of bit; -- Error: 'array' is not a predefined type

-- Right: Define type first
type bit_array is array (0 to 7) of bit;
signal data : bit_array;

Quick Reference

Remember these key points when working with arrays in VHDL:

• Define array types with type.
• Use consistent index ranges and directions.
• Arrays hold elements of the same type.
• Assign values using aggregate syntax like (others => '0') or explicit index assignments.

Key Takeaways

Always define a custom array type before declaring signals or variables of that array.

Use consistent index ranges and directions to avoid confusion and errors.

Arrays group multiple elements of the same type for easier data handling.

Assign values to arrays using aggregate syntax or explicit index assignments.

Avoid mixing incompatible types like std_logic_vector and custom arrays without conversion.