VHDL Code for 2-to-4 Decoder: Syntax and Example

A 2-to-4 decoder in VHDL converts 2 input bits into 4 output lines, each representing one input combination. You can write it using a process block or with-select statement to assign outputs based on inputs.

Syntax

The basic syntax for a 2-to-4 decoder in VHDL involves defining an entity with 2 inputs and 4 outputs. Inside the architecture, you use a process block or with-select statement to assign output lines based on the input values.

• entity: Declares input and output ports.
• architecture: Contains the logic to decode inputs.
• process: Reacts to input changes and sets outputs.
• with-select: Alternative to process for conditional output assignment.

vhdl

entity decoder_2to4 is
    Port (
        A : in std_logic_vector(1 downto 0);
        Y : out std_logic_vector(3 downto 0)
    );
end decoder_2to4;

architecture Behavioral of decoder_2to4 is
begin
    process(A)
    begin
        case A is
            when "00" => Y <= "0001";
            when "01" => Y <= "0010";
            when "10" => Y <= "0100";
            when "11" => Y <= "1000";
            when others => Y <= "0000";
        end case;
    end process;
end Behavioral;

Example

This example shows a complete 2-to-4 decoder using a process block. It sets one output line high based on the 2-bit input, turning others low. This is useful for selecting one of four options based on two input bits.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder_2to4 is
    Port (
        A : in std_logic_vector(1 downto 0);
        Y : out std_logic_vector(3 downto 0)
    );
end decoder_2to4;

architecture Behavioral of decoder_2to4 is
begin
    process(A)
    begin
        case A is
            when "00" => Y <= "0001";
            when "01" => Y <= "0010";
            when "10" => Y <= "0100";
            when "11" => Y <= "1000";
            when others => Y <= "0000";
        end case;
    end process;
end Behavioral;

Common Pitfalls

Common mistakes when writing a 2-to-4 decoder in VHDL include:

• Not covering all input cases, leading to undefined outputs.
• Forgetting to use std_logic_vector for inputs and outputs.
• Assigning multiple outputs high at once instead of only one.
• Using incorrect bit order or mismatched vector sizes.

Always use a case statement or with-select to clearly define output for every input.

vhdl

wrong: 
process(A)
begin
    if A = "00" then
        Y <= "0001";
    elsif A = "01" then
        Y <= "0011"; -- wrong: two outputs high
    else
        Y <= "0000"; -- missing cases
    end if;
end process;

correct:
process(A)
begin
    case A is
        when "00" => Y <= "0001";
        when "01" => Y <= "0010";
        when "10" => Y <= "0100";
        when "11" => Y <= "1000";
        when others => Y <= "0000";
    end case;
end process;

Quick Reference

Remember these tips when coding a 2-to-4 decoder in VHDL:

• Use std_logic_vector(1 downto 0) for 2-bit input.
• Use std_logic_vector(3 downto 0) for 4-bit output.
• Use case or with-select to assign outputs.
• Only one output bit should be '1' at a time.
• Cover all input combinations to avoid latches or unknown outputs.

Key Takeaways

A 2-to-4 decoder converts 2 input bits into 4 outputs with only one output active at a time.

Use a process with a case statement or a with-select statement to assign outputs based on inputs.

Always cover all input cases to avoid undefined outputs.

Use std_logic_vector types for inputs and outputs to match bit widths.

Avoid assigning multiple outputs high simultaneously to ensure correct decoding.