How to Use Port Map in VHDL: Syntax and Example

In VHDL, port map is used to connect the ports of a component instance to signals or other ports in your design. It allows you to specify which signals correspond to each port of the component by name or position, enabling modular and reusable hardware design.

Syntax

The port map statement connects component ports to signals or other ports. It follows this pattern:

• component_instance_name : component_name port map (port1 => signal1, port2 => signal2, ...);
• component_instance_name: a unique name for this instance.
• component_name: the name of the component you want to use.
• port map: keyword to start the connection.
• port1 => signal1: connects the component's port1 to signal1 in your design.

vhdl

component_instance_name : component_name port map (
    port1 => signal1,
    port2 => signal2,
    port3 => signal3
);

Example

This example shows how to instantiate a simple AND gate component and connect its ports using port map. It demonstrates modular design by reusing the AND gate component.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

entity TopLevel is
    Port ( X : in STD_LOGIC;
           Z : in STD_LOGIC;
           F : out STD_LOGIC);
end TopLevel;

architecture Structural of TopLevel is
    signal temp : STD_LOGIC;
begin
    U1 : AndGate port map (
        A => X,
        B => Z,
        Y => temp
    );
    F <= temp;
end Structural;

Common Pitfalls

Common mistakes when using port map include:

• Not matching port names exactly when using named association.
• Mixing positional and named associations incorrectly.
• Forgetting to declare signals connected to output ports.
• Using positional mapping but giving ports in wrong order.

Always prefer named mapping for clarity and fewer errors.

vhdl

-- Wrong: positional mapping with wrong order
U1 : AndGate port map (Z, X, temp); -- ports are (A, B, Y), order is wrong

-- Right: named mapping
U1 : AndGate port map (
    A => X,
    B => Z,
    Y => temp
);

Quick Reference

Term	Description
component_instance_name	Unique name for the component instance
component_name	Name of the component being instantiated
port map	Keyword to connect ports to signals
port => signal	Named association connecting a port to a signal
Positional mapping	Connecting ports by position without names (less safe)

Key Takeaways

Use port map to connect component ports to signals by name or position.

Named port mapping is clearer and less error-prone than positional mapping.

Ensure signal types match the component port types when connecting.

Always declare signals for outputs connected via port map.

Check port names carefully to avoid mismatches in named associations.