Resolved and Unresolved Types in VHDL: Explanation and Examples

In VHDL, an unresolved type is a data type that does not automatically handle multiple drivers on a signal, while a resolved type uses a resolution function to combine values from multiple drivers into a single value. Resolved types are essential for signals driven by more than one source, ensuring a defined final value.

How It Works

Think of signals in VHDL like wires in a circuit. Sometimes, only one source drives a wire, so the value is clear. This is like an unresolved type, where the signal holds a single value without any automatic way to handle conflicts.

But what if multiple sources try to drive the same wire? This can cause confusion, like two people trying to speak at once. A resolved type uses a special rule called a resolution function to decide the final value by combining all inputs. This is like having a referee who listens to all voices and picks the right answer.

In VHDL, unresolved types are simple and used when only one driver exists. Resolved types are needed when multiple drivers can affect a signal, such as in buses or tri-state logic.

Example

This example shows an unresolved type bit and a resolved type std_logic with a resolution function that handles multiple drivers.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity resolved_example is
    Port (
        a : in std_logic;
        b : in std_logic;
        c : out std_logic
    );
end resolved_example;

architecture Behavioral of resolved_example is
    signal temp : std_logic;
begin
    -- temp is driven by two sources a and b
    temp <= a when a /= 'Z' else b;
    c <= temp;
end Behavioral;

When to Use

Use unresolved types when a signal has only one driver, such as internal variables or simple signals. They are straightforward and efficient.

Use resolved types when signals can have multiple drivers, like shared buses or tri-state lines. The resolution function ensures the final signal value is consistent and predictable, avoiding conflicts.

For example, in hardware designs with multiple components driving a common bus, resolved types prevent errors by combining all inputs safely.

Key Points

• Unresolved types hold a single value and do not handle multiple drivers.
• Resolved types use resolution functions to combine multiple driver values into one.
• Use resolved types for signals driven by multiple sources to avoid conflicts.
• Common resolved types in VHDL include std_logic and std_logic_vector.
• Unresolved types are simpler and used when only one driver exists.

Key Takeaways

Resolved types in VHDL combine multiple drivers using resolution functions to produce a single signal value.

Unresolved types do not handle multiple drivers and are used when only one source drives a signal.

Use resolved types for shared signals like buses to avoid conflicts and undefined behavior.

Common resolved types include std_logic and std_logic_vector with built-in resolution functions.

Choose unresolved types for simple, single-driver signals to keep designs efficient.