How to Write Synchronous Reset in VHDL: Syntax and Example

To write a synchronous reset in VHDL, include the reset condition inside the clocked process and check it after the clock edge. Use an if statement inside the process triggered by the clock to reset signals only when the clock ticks.

Syntax

A synchronous reset is written inside a clocked process. The reset condition is checked after detecting a clock edge, usually with if rising_edge(clk). Inside this, use if reset = '1' to set signals to their reset values.

• process(clk): Defines a process triggered by the clock.
• if rising_edge(clk): Checks for the clock's rising edge.
• if reset = '1': Checks if reset is active synchronously.
• else: Normal operation when reset is not active.

vhdl

process(clk) is
begin
  if rising_edge(clk) then
    if reset = '1' then
      -- reset signals here
    else
      -- normal operation
    end if;
  end if;
end process;

Example

This example shows a simple 4-bit counter with a synchronous reset. When reset is '1' at the clock's rising edge, the counter resets to zero. Otherwise, it increments by one.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sync_reset_counter is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    count : out unsigned(3 downto 0)
  );
end sync_reset_counter;

architecture Behavioral of sync_reset_counter is
  signal counter_reg : unsigned(3 downto 0) := (others => '0');
begin
  process(clk) is
  begin
    if rising_edge(clk) then
      if reset = '1' then
        counter_reg <= (others => '0');
      else
        counter_reg <= counter_reg + 1;
      end if;
    end if;
  end process;

  count <= counter_reg;
end Behavioral;

Output

On each rising clock edge, if reset='1', count resets to 0000; otherwise, count increments by 1.

Common Pitfalls

Common mistakes when writing synchronous resets include:

• Placing the reset check outside the clock edge condition, which makes it asynchronous.
• Forgetting to check the clock edge before the reset condition.
• Using asynchronous reset signals in a synchronous reset style process.

Always ensure the reset condition is inside the if rising_edge(clk) block.

vhdl

process(clk) is
begin
  -- Wrong: reset checked outside clock edge
  if reset = '1' then
    counter_reg <= (others => '0');
  elsif rising_edge(clk) then
    counter_reg <= counter_reg + 1;
  end if;
end process;

-- Correct:
process(clk) is
begin
  if rising_edge(clk) then
    if reset = '1' then
      counter_reg <= (others => '0');
    else
      counter_reg <= counter_reg + 1;
    end if;
  end if;
end process;

Quick Reference

Remember these tips for synchronous reset in VHDL:

• Check reset inside the clock edge condition.
• Use if rising_edge(clk) for clock detection.
• Reset signals to default values when reset is active.
• Keep reset synchronous to avoid timing issues.

Key Takeaways

Always place the synchronous reset check inside the clock edge condition.

Use if rising_edge(clk) to detect clock edges before checking reset.

Reset signals to default values only when reset is active during the clock edge.

Avoid checking reset outside the clock edge to keep it synchronous.

Test your design to confirm reset behavior matches expectations.