How to Declare Entity in VHDL: Syntax and Example

In VHDL, you declare an entity to define the interface of a hardware component using the entity keyword followed by its name and port definitions inside a port block. The entity declaration specifies inputs and outputs but does not describe behavior.

Syntax

An entity declaration in VHDL starts with the entity keyword, followed by the entity name and the is keyword. Inside, the port block lists input and output signals with their directions and types. The declaration ends with end entity_name;.

• entity: starts the declaration
• entity_name: the name of the component
• port: defines inputs and outputs
• in or out: signal direction
• std_logic: common signal type for single-bit signals

vhdl

entity entity_name is
    port (
        input1 : in std_logic;
        output1 : out std_logic
    );
end entity_name;

Example

This example declares a simple entity named and_gate with two inputs and one output. It shows how to define the interface of a 2-input AND gate.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate is
    port (
        a : in std_logic;
        b : in std_logic;
        y : out std_logic
    );
end and_gate;

Common Pitfalls

Common mistakes when declaring entities include:

• Forgetting the port keyword or parentheses around ports.
• Missing signal directions (in or out).
• Using incorrect or undefined signal types.
• Not matching the end statement with the entity name.

Always ensure the syntax is exact to avoid compilation errors.

vhdl

entity wrong_entity is
    a : in std_logic;  -- Missing port keyword and parentheses
end wrong_entity;

-- Correct way:
entity correct_entity is
    port (
        a : in std_logic
    );
end correct_entity;

Quick Reference

Remember these key points when declaring an entity:

• Start with entity and end with end entity_name;.
• Use port block to list all inputs and outputs.
• Specify direction: in for inputs, out for outputs.
• Use standard types like std_logic for signals.

Key Takeaways

Declare an entity with the entity keyword followed by its name and a port block.

Ports must specify signal names, directions (in or out), and types like std_logic.

The entity defines the interface only; behavior is described separately in an architecture.

Always match the end statement with the entity name exactly.

Avoid syntax errors by including the port keyword and parentheses around port declarations.