VHDL Code for SIPO Shift Register: Syntax and Example

A Serial-In Parallel-Out (SIPO) shift register in VHDL can be coded using a process triggered by a clock signal that shifts input bits into a register and outputs them in parallel. Use a std_logic_vector to hold the shifted bits and update it on each clock cycle with the serial input.

Syntax

The basic syntax for a SIPO shift register in VHDL includes a process block sensitive to the clock, a std_logic_vector signal to store bits, and logic to shift bits on each clock edge.

• clk: Clock signal triggering the shift.
• serial_in: Serial input bit to be shifted in.
• parallel_out: Vector output showing all bits in parallel.
• shift_reg: Internal register holding the shifted bits.

vhdl

process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= shift_reg(shift_reg'length-2 downto 0) & serial_in;
  end if;
end process;

Example

This example shows a 4-bit SIPO shift register that takes a serial input bit and outputs the 4 bits in parallel after shifting on each clock pulse.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sipo_shift_register is
  Port (
    clk         : in  std_logic;
    serial_in   : in  std_logic;
    parallel_out: out std_logic_vector(3 downto 0)
  );
end sipo_shift_register;

architecture Behavioral of sipo_shift_register is
  signal shift_reg : std_logic_vector(3 downto 0) := (others => '0');
begin
  process(clk)
  begin
    if rising_edge(clk) then
      shift_reg <= shift_reg(2 downto 0) & serial_in;
    end if;
  end process;

  parallel_out <= shift_reg;
end Behavioral;

Output

On each rising clock edge, the serial input bit is shifted into the register, and the 4-bit parallel output updates accordingly.

Common Pitfalls

Common mistakes when coding a SIPO shift register include:

• Not using rising_edge(clk) to detect clock edges, which can cause incorrect shifting.
• Incorrect indexing of the std_logic_vector when shifting bits, leading to data loss or wrong order.
• Forgetting to initialize the shift register, which can cause unknown outputs at start.

vhdl

process(clk)
begin
  if clk = '1' then  -- Wrong: level sensitive, not edge sensitive
    shift_reg <= shift_reg(3 downto 1) & serial_in; -- Correct order for shifting left
  end if;
end process;

-- Correct version:
process(clk)
begin
  if rising_edge(clk) then
    shift_reg <= shift_reg(2 downto 0) & serial_in;
  end if;
end process;

Quick Reference

Term	Description
clk	Clock input signal triggering shifts
serial_in	Single bit input shifted into register
shift_reg	Internal vector holding shifted bits
parallel_out	Output vector showing all bits in parallel
rising_edge(clk)	Detects clock's rising edge for synchronous operation

Key Takeaways

Use a process triggered by rising_edge(clk) to shift bits synchronously.

Shift the register vector left or right correctly to maintain bit order.

Initialize the shift register to avoid unknown startup values.

Output the internal register as parallel data for SIPO functionality.

Avoid level-sensitive clock checks to prevent timing errors.