VHDL Code for 3-to-8 Decoder: Syntax and Example

A 3-to-8 decoder in VHDL converts 3 input bits into 8 output lines, each representing one unique input combination. You can write it using a with-select statement or a process block with case statements to assign outputs based on inputs.

Syntax

A 3-to-8 decoder has 3 input bits and 8 output bits. The output line corresponding to the binary value of the input is set to '1', and all others are '0'.

Key parts:

• entity: declares inputs and outputs
• architecture: describes the logic
• with-select or process-case: assigns output based on input

vhdl

entity decoder3to8 is
    Port ( input : in std_logic_vector(2 downto 0);
           output : out std_logic_vector(7 downto 0));
end decoder3to8;

architecture Behavioral of decoder3to8 is
begin
    with input select
        output <= "00000001" when "000",
                  "00000010" when "001",
                  "00000100" when "010",
                  "00001000" when "011",
                  "00010000" when "100",
                  "00100000" when "101",
                  "01000000" when "110",
                  "10000000" when "111",
                  "00000000" when others;
end Behavioral;

Example

This example shows a complete 3-to-8 decoder using a with-select statement. The output line matching the input binary value is set to '1'.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder3to8 is
    Port ( input : in std_logic_vector(2 downto 0);
           output : out std_logic_vector(7 downto 0));
end decoder3to8;

architecture Behavioral of decoder3to8 is
begin
    with input select
        output <= "00000001" when "000",
                  "00000010" when "001",
                  "00000100" when "010",
                  "00001000" when "011",
                  "00010000" when "100",
                  "00100000" when "101",
                  "01000000" when "110",
                  "10000000" when "111",
                  "00000000" when others;
end Behavioral;

Output

When input = "010", output = "00000100" (only the third output bit is '1')

Common Pitfalls

Common mistakes include:

• Not covering all input cases, missing when others clause causes simulation errors.
• Assigning multiple output bits to '1' at the same time, which breaks decoder logic.
• Using incorrect bit order in output vector.

Always ensure only one output bit is '1' for each input.

vhdl

architecture WrongExample of decoder3to8 is
begin
    with input select
        output <= "00000011" when "000", -- Wrong: two bits '1'
                  "00000010" when "001",
                  "00000100" when "010",
                  "00001000" when "011",
                  "00010000" when "100",
                  "00100000" when "101",
                  "01000000" when "110",
                  "10000000" when "111",
                  "00000000" when others;
end WrongExample;

architecture CorrectExample of decoder3to8 is
begin
    with input select
        output <= "00000001" when "000",
                  "00000010" when "001",
                  "00000100" when "010",
                  "00001000" when "011",
                  "00010000" when "100",
                  "00100000" when "101",
                  "01000000" when "110",
                  "10000000" when "111",
                  "00000000" when others;
end CorrectExample;

Quick Reference

Remember these tips for 3-to-8 decoder in VHDL:

• Input is 3 bits, output is 8 bits.
• Only one output bit is '1' at a time.
• Use with-select or case inside a process.
• Always include when others to cover unexpected inputs.

Key Takeaways

A 3-to-8 decoder sets exactly one output bit high based on 3-bit input.

Use a with-select or case statement to assign outputs clearly.

Always include a when others clause to handle unexpected inputs safely.

Avoid assigning multiple output bits to '1' simultaneously to keep decoder logic correct.

Check bit order carefully to match input combinations with correct output lines.