How to Create Package in VHDL: Syntax and Example

In VHDL, you create a package using the package and package body constructs to group reusable declarations like types, constants, and functions. The package declares the interface, and the package body defines the implementation of any subprograms.

Syntax

A VHDL package is created in two parts: the package declaration and the package body. The package declares types, constants, signals, and subprogram headers. The package body contains the actual code for subprograms like functions or procedures.

• package <name> is: Start of package declaration.
• declarations: Types, constants, signals, subprogram headers.
• end package <name>;: End of package declaration.
• package body <name> is: Start of package body.
• subprogram implementations: Code for declared functions/procedures.
• end package body <name>;: End of package body.

vhdl

package MyPackage is
    constant WIDTH : integer := 8;
    type ByteArray is array (0 to WIDTH-1) of std_logic;
    function to_upper(c : character) return character;
end package MyPackage;

package body MyPackage is
    function to_upper(c : character) return character is
    begin
        if c >= 'a' and c <= 'z' then
            return character'val(character'pos(c) - 32);
        else
            return c;
        end if;
    end function to_upper;
end package body MyPackage;

Example

This example shows a package named MyPackage that defines a constant, a type, and a function to convert a lowercase character to uppercase. The package body implements the function logic.

vhdl

library ieee;
use ieee.std_logic_1164.all;

package MyPackage is
    constant WIDTH : integer := 8;
    type ByteArray is array (0 to WIDTH-1) of std_logic;
    function to_upper(c : character) return character;
end package MyPackage;

package body MyPackage is
    function to_upper(c : character) return character is
    begin
        if c >= 'a' and c <= 'z' then
            return character'val(character'pos(c) - 32);
        else
            return c;
        end if;
    end function to_upper;
end package body MyPackage;

-- Usage example in an architecture
library ieee;
use ieee.std_logic_1164.all;
use work.MyPackage.all;

entity Demo is
end entity Demo;

architecture Behavioral of Demo is
begin
    process
        variable ch : character := 'b';
        variable up : character;
    begin
        up := to_upper(ch);
        report "Uppercase of '" & ch & "' is '" & up & "'";
        wait;
    end process;
end Behavioral;

Output

Uppercase of 'b' is 'B'

Common Pitfalls

Common mistakes when creating packages in VHDL include:

• Forgetting to create the package body when the package declares functions or procedures.
• Not using use <package_name>.all; to access package contents in other files.
• Declaring subprograms in the package but not implementing them in the package body.
• Using inconsistent names between the package declaration and package body.

vhdl

package WrongPackage is
    function add_one(x : integer) return integer;
end package WrongPackage;

-- Missing package body leads to errors when calling add_one

-- Correct way:
package body WrongPackage is
    function add_one(x : integer) return integer is
    begin
        return x + 1;
    end function add_one;
end package body WrongPackage;

Quick Reference

Remember these tips when working with VHDL packages:

• Use package to declare reusable items.
• Use package body to define function/procedure code.
• Include use <package>.all; to access package contents.
• Keep package and package body names identical.
• Compile package before using it in other designs.

Key Takeaways

Create a package with package and implement functions in package body.

Declare reusable constants, types, and subprogram headers inside the package.

Always implement declared functions or procedures in the package body to avoid errors.

Use use <package>.all; to access package contents in other files.

Ensure package and package body names match exactly.