VHDL Code for Demultiplexer: Syntax and Example

A demultiplexer in VHDL routes one input to one of many outputs based on select lines using if or case statements inside a process. The basic code includes input, output ports, select signals, and logic to assign the input to the selected output line.

Syntax

The basic syntax for a demultiplexer in VHDL uses an entity to define inputs, outputs, and select lines. Inside the architecture, a process block uses a case statement on the select signal to route the input to the correct output.

• entity: Defines input, output, and select ports.
• architecture: Contains the logic to assign input to outputs.
• process: Reacts to changes in input or select signals.
• case: Chooses which output gets the input based on select.

vhdl

entity Demux is
    Port (
        input : in std_logic;
        sel : in std_logic_vector(1 downto 0);
        output : out std_logic_vector(3 downto 0)
    );
end Demux;

architecture Behavioral of Demux is
begin
    process(input, sel)
    begin
        output <= (others => '0'); -- default all outputs to 0
        case sel is
            when "00" => output(0) <= input;
            when "01" => output(1) <= input;
            when "10" => output(2) <= input;
            when "11" => output(3) <= input;
            when others => output <= (others => '0');
        end case;
    end process;
end Behavioral;

Example

This example shows a 1-to-4 demultiplexer. The input is routed to one of four output lines based on the 2-bit sel signal. When sel changes, the corresponding output line gets the input value, and others are zero.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Demux_1to4 is
    Port (
        input : in std_logic;
        sel : in std_logic_vector(1 downto 0);
        output : out std_logic_vector(3 downto 0)
    );
end Demux_1to4;

architecture Behavioral of Demux_1to4 is
begin
    process(input, sel)
    begin
        output <= (others => '0');
        case sel is
            when "00" => output(0) <= input;
            when "01" => output(1) <= input;
            when "10" => output(2) <= input;
            when "11" => output(3) <= input;
            when others => output <= (others => '0');
        end case;
    end process;
end Behavioral;

Output

When sel = "00" and input = '1', output = "1000"
When sel = "01" and input = '1', output = "0100"
When sel = "10" and input = '1', output = "0010"
When sel = "11" and input = '1', output = "0001"
When input = '0', output = "0000" regardless of sel

Common Pitfalls

Common mistakes when writing VHDL demultiplexers include:

• Not resetting outputs to zero before assigning the selected output, causing multiple outputs to be high.
• Forgetting to include all select cases, leading to latches or unintended behavior.
• Using if statements without an else branch, which can cause incomplete assignments.
• Not including all signals in the process sensitivity list, which can cause simulation mismatches.

vhdl

Wrong way (missing default zero assignment):
process(input, sel)
begin
    case sel is
        when "00" => output(0) <= input;
        when "01" => output(1) <= input;
        when "10" => output(2) <= input;
        when "11" => output(3) <= input;
        when others => null;
    end case;
end process;

Right way (reset outputs first):
process(input, sel)
begin
    output <= (others => '0');
    case sel is
        when "00" => output(0) <= input;
        when "01" => output(1) <= input;
        when "10" => output(2) <= input;
        when "11" => output(3) <= input;
        when others => output <= (others => '0');
    end case;
end process;

Quick Reference

Remember these tips when coding a demultiplexer in VHDL:

• Use std_logic_vector for multiple outputs and select lines.
• Always reset outputs to zero before assigning the selected output.
• Use a case statement for clear select logic.
• Include all possible select values to avoid latches.
• Include all signals in the process sensitivity list.

Key Takeaways

A demultiplexer routes one input to one of many outputs based on select signals using a case statement.

Always reset all outputs to zero before assigning the selected output to avoid multiple active outputs.

Include all select cases and a default to prevent unintended latches or simulation mismatches.

Use a process with input and select signals in the sensitivity list for correct simulation behavior.

Use std_logic_vector for outputs and select lines to handle multiple bits cleanly.