VHDL Code for Vending Machine FSM: Simple Example and Guide
A vending machine FSM in
VHDL uses states to track inserted coins and dispense items. You define states, inputs, and outputs, then write a process with a case statement to handle transitions and actions based on coin inputs and selections.Syntax
The vending machine FSM in VHDL typically includes:
- Entity: Defines inputs (coins, selection) and outputs (dispense, change).
- Architecture: Contains the state machine logic.
- States: Represent different amounts of money inserted.
- Process block: Uses a
casestatement to handle state transitions and outputs.
vhdl
entity vending_machine is
Port (
clk : in std_logic;
reset : in std_logic;
coin_5 : in std_logic; -- 5 cents coin input
coin_10 : in std_logic; -- 10 cents coin input
select : in std_logic; -- item selection
dispense : out std_logic;
change : out std_logic_vector(3 downto 0) -- change amount
);
end vending_machine;
architecture Behavioral of vending_machine is
type state_type is (S0, S5, S10, S15, DISPENSE);
signal state, next_state : state_type;
begin
process(clk, reset)
begin
if reset = '1' then
state <= S0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, coin_5, coin_10, select)
begin
dispense <= '0';
change <= (others => '0');
case state is
when S0 =>
if coin_5 = '1' then
next_state <= S5;
elsif coin_10 = '1' then
next_state <= S10;
else
next_state <= S0;
end if;
when S5 =>
if coin_5 = '1' then
next_state <= S10;
elsif coin_10 = '1' then
next_state <= S15;
else
next_state <= S5;
end if;
when S10 =>
if coin_5 = '1' then
next_state <= S15;
elsif coin_10 = '1' then
next_state <= DISPENSE;
else
next_state <= S10;
end if;
when S15 =>
if select = '1' then
dispense <= '1';
change <= "0001"; -- 1 unit change
next_state <= S0;
else
next_state <= S15;
end if;
when DISPENSE =>
dispense <= '1';
change <= "0000";
next_state <= S0;
when others =>
next_state <= S0;
end case;
end process;
end Behavioral;Example
This example shows a simple vending machine FSM that accepts 5 and 10 cent coins, tracks the total inserted, and dispenses an item when enough money is inserted and the selection is made. It also returns change if needed.
vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vending_machine is
Port (
clk : in std_logic;
reset : in std_logic;
coin_5 : in std_logic;
coin_10 : in std_logic;
select : in std_logic;
dispense : out std_logic;
change : out std_logic_vector(3 downto 0)
);
end vending_machine;
architecture Behavioral of vending_machine is
type state_type is (S0, S5, S10, S15, DISPENSE);
signal state, next_state : state_type;
begin
process(clk, reset)
begin
if reset = '1' then
state <= S0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, coin_5, coin_10, select)
begin
dispense <= '0';
change <= (others => '0');
case state is
when S0 =>
if coin_5 = '1' then
next_state <= S5;
elsif coin_10 = '1' then
next_state <= S10;
else
next_state <= S0;
end if;
when S5 =>
if coin_5 = '1' then
next_state <= S10;
elsif coin_10 = '1' then
next_state <= S15;
else
next_state <= S5;
end if;
when S10 =>
if coin_5 = '1' then
next_state <= S15;
elsif coin_10 = '1' then
next_state <= DISPENSE;
else
next_state <= S10;
end if;
when S15 =>
if select = '1' then
dispense <= '1';
change <= "0001"; -- 1 unit change
next_state <= S0;
else
next_state <= S15;
end if;
when DISPENSE =>
dispense <= '1';
change <= "0000";
next_state <= S0;
when others =>
next_state <= S0;
end case;
end process;
end Behavioral;Output
No direct console output; the FSM changes states and sets outputs 'dispense' and 'change' signals accordingly during simulation.
Common Pitfalls
Common mistakes when writing a vending machine FSM in VHDL include:
- Not handling the
resetproperly, causing the FSM to start in an undefined state. - Forgetting to update the
next_statein all branches, which can cause latches or unintended behavior. - Not using synchronous state updates with the clock, leading to glitches.
- Mixing combinational and sequential logic incorrectly inside processes.
vhdl
process(clk, reset)
begin
if reset = '1' then
state <= S0;
elsif rising_edge(clk) then
-- Missing state update here causes latch
end if;
end process;
-- Correct way:
process(clk, reset)
begin
if reset = '1' then
state <= S0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;Quick Reference
Tips for writing vending machine FSM in VHDL:
- Define clear states representing money inserted.
- Use a clocked process for state updates.
- Use a combinational process for next state logic and outputs.
- Reset the FSM to a known state.
- Test with different coin inputs and selections.
Key Takeaways
Define states clearly to represent the amount of money inserted in the vending machine.
Use a clocked process to update the current state synchronously with the clock signal.
Separate next state logic and output logic in a combinational process using a case statement.
Always include a reset signal to initialize the FSM to a known state.
Test your FSM thoroughly with all coin and selection input combinations to avoid unexpected behavior.