VHDL How to Convert std_logic_vector to Integer

Use the to_integer(unsigned(your_std_logic_vector)) function from the numeric_std library to convert a std_logic_vector to an integer in VHDL.

Examples

Input00000001

Output1

Input00001010

Output10

Input11111111

Output255

How to Think About It

To convert a std_logic_vector to an integer, first treat the vector as an unsigned number using the unsigned type conversion, then convert that unsigned value to an integer with to_integer. This ensures the bits are interpreted as a binary number.

Algorithm

1

Get the std_logic_vector input.

2

Convert the std_logic_vector to unsigned type.

3

Convert the unsigned value to an integer using to_integer.

4

Return the integer result.

Code

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity convert_example is
end convert_example;

architecture behavior of convert_example is
  signal slv : std_logic_vector(7 downto 0) := "00001010"; -- 10 in binary
  signal result : integer;
begin
  process
  begin
    result <= to_integer(unsigned(slv));
    report "Converted integer: " & integer'image(result);
    wait;
  end process;
end behavior;

Output

Converted integer: 10

Dry Run

Let's trace converting std_logic_vector "00001010" to integer.

1

Input std_logic_vector

slv = "00001010"

2

Convert to unsigned

unsigned(slv) = 10 (binary interpreted as unsigned)

3

Convert to integer

to_integer(unsigned(slv)) = 10

Step	Value
Input	00001010
Unsigned	10
Integer	10

Why This Works

Step 1: Use unsigned conversion

The unsigned type tells VHDL to treat the bits as a positive binary number.

Step 2: Use to_integer function

The to_integer function converts the unsigned binary number to a normal integer value.

Alternative Approaches

Using numeric_std signed conversion

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity convert_signed is
end convert_signed;

architecture behavior of convert_signed is
  signal slv : std_logic_vector(7 downto 0) := "11111111"; -- -1 in signed
  signal result : integer;
begin
  process
  begin
    result <= to_integer(signed(slv));
    report "Converted signed integer: " & integer'image(result);
    wait;
  end process;
end behavior;

Use this if the std_logic_vector represents a signed number; otherwise, use unsigned.

Manual binary to integer conversion

vhdl

library ieee;
use ieee.std_logic_1164.all;

entity manual_convert is
end manual_convert;

architecture behavior of manual_convert is
  signal slv : std_logic_vector(3 downto 0) := "1010"; -- 10 in binary
  signal result : integer := 0;
begin
  process
  begin
    result := 0;
    for i in slv'range loop
      if slv(i) = '1' then
        result := result + 2**(slv'length - 1 - i);
      end if;
    end loop;
    report "Manual converted integer: " & integer'image(result);
    wait;
  end process;
end behavior;

This method is less efficient and more verbose but shows how conversion works bit by bit.

Complexity: O(n) time, O(1) space

Time Complexity

Conversion scans each bit once, so it takes linear time relative to the vector length.

Space Complexity

No extra memory is needed besides the integer result, so space is constant.

Which Approach is Fastest?

Using to_integer(unsigned()) is fastest and simplest; manual bitwise conversion is slower and verbose.

Approach	Time	Space	Best For
to_integer(unsigned())	O(n)	O(1)	Standard unsigned conversion
to_integer(signed())	O(n)	O(1)	Signed number conversion
Manual bitwise	O(n)	O(1)	Learning or custom conversion logic