VhdlHow-ToBeginner · 4 min read

How to Use Package in VHDL: Syntax and Example

In VHDL, you use a package to group related declarations like types, constants, and functions. To use a package, declare it with package and package body, then include it in your design with use statements.

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Syntax

A VHDL package groups reusable declarations. You define it with package and implement details in package body. To use it in your design, add use work.package_name.all;.

package package_name is: Starts the package declaration.
package body package_name is: Contains implementations like function bodies.
use work.package_name.all;: Makes package contents available in your design.

vhdl

package my_pkg is
  constant PI : real := 3.14159;
  function square(x : real) return real;
end package my_pkg;

package body my_pkg is
  function square(x : real) return real is
  begin
    return x * x;
  end function square;
end package body my_pkg;

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Example

This example shows how to define a package with a constant and a function, then use it in an entity to calculate the square of a number.

vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_pkg.all;

entity test_pkg is
  port(
    input_val : in real;
    output_val : out real
  );
end entity test_pkg;

architecture rtl of test_pkg is
begin
  process(input_val)
  begin
    output_val <= square(input_val);
  end process;
end architecture rtl;

Output

When input_val = 3.0, output_val = 9.0

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Common Pitfalls

Common mistakes when using packages in VHDL include:

Forgetting to compile the package before using it.
Not including the use work.package_name.all; statement in your design.
Defining functions only in the package declaration without implementing them in the package body.
Using package names incorrectly or with wrong library prefixes.

vhdl

-- Wrong: Using package without 'use' statement
entity wrong_use is
  port(input_val : in real; output_val : out real);
end entity wrong_use;

architecture rtl of wrong_use is
begin
  process(input_val)
  begin
    output_val <= square(input_val); -- Error: square not found
  end process;
end architecture rtl;

-- Right: Include 'use work.my_pkg.all;'
library ieee;
use ieee.std_logic_1164.all;
use work.my_pkg.all;

entity right_use is
  port(input_val : in real; output_val : out real);
end entity right_use;

architecture rtl of right_use is
begin
  process(input_val)
  begin
    output_val <= square(input_val); -- Works fine
  end process;
end architecture rtl;

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Quick Reference

Define package: package name is ... end package;
Implement package body: package body name is ... end package body;
Use package: use work.name.all;
Compile order: Package first, then designs using it.

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Key Takeaways

Define reusable declarations inside a package and implement functions in the package body.

Always compile the package before using it in your design files.

Include the statement 'use work.package_name.all;' to access package contents.

Avoid missing implementations or wrong library references to prevent errors.

Packages help organize and reuse code efficiently in VHDL projects.