VHDL Code for Clock Divider: Syntax and Example

A clock divider in VHDL reduces the frequency of an input clock by counting input cycles and toggling an output clock. Use a process with a counter that increments on each rising edge of the input clock and toggles the output clock when the count reaches half the division factor, as shown in the clock_divider example.

Syntax

The basic syntax for a clock divider in VHDL uses a process triggered on the rising edge of the input clock. Inside, a counter variable increments each clock cycle. When the counter reaches a set value (half the division factor), the output clock signal toggles and the counter resets.

• clk_in: input clock signal
• clk_out: output divided clock signal
• counter: counts input clock cycles
• DIVIDE_BY: constant for division factor

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clock_divider is
    Port (
        clk_in  : in  std_logic;
        reset   : in  std_logic;
        clk_out : out std_logic
    );
end clock_divider;

architecture Behavioral of clock_divider is
    constant DIVIDE_BY : integer := 4; -- divide clock by 4
    signal counter : integer range 0 to DIVIDE_BY/2 := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in, reset)
    begin
        if reset = '1' then
            counter <= 0;
            clk_div <= '0';
        elsif rising_edge(clk_in) then
            if counter = (DIVIDE_BY/2 - 1) then
                clk_div <= not clk_div;
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end Behavioral;

Example

This example divides an input clock by 4. The output clock frequency is one fourth of the input clock frequency. The process counts input clock edges and toggles the output clock every 2 input cycles.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clock_divider is
    Port (
        clk_in  : in  std_logic;
        reset   : in  std_logic;
        clk_out : out std_logic
    );
end clock_divider;

architecture Behavioral of clock_divider is
    constant DIVIDE_BY : integer := 4;
    signal counter : integer range 0 to DIVIDE_BY/2 := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in, reset)
    begin
        if reset = '1' then
            counter <= 0;
            clk_div <= '0';
        elsif rising_edge(clk_in) then
            if counter = (DIVIDE_BY/2 - 1) then
                clk_div <= not clk_div;
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end Behavioral;

Output

The output clock (clk_out) frequency is clk_in frequency divided by 4, toggling every 2 input clock cycles.

Common Pitfalls

Common mistakes when writing a clock divider in VHDL include:

• Not resetting the counter and output clock properly, causing unpredictable output.
• Using an odd division factor without handling the half-cycle correctly, leading to uneven clock pulses.
• Incrementing the counter incorrectly or toggling the output clock at the wrong count.
• Forgetting to use rising_edge(clk_in) for synchronous counting.

vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity wrong_divider is
    Port (
        clk_in  : in  std_logic;
        clk_out : out std_logic
    );
end wrong_divider;

architecture Behavioral of wrong_divider is
    signal counter : integer := 0;
    signal clk_div : std_logic := '0';
begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then -- FIXED: use edge detection
            counter <= counter + 1;
            if counter = 2 then
                clk_div <= not clk_div;
                counter <= 0;
            end if;
        end if;
    end process;

    clk_out <= clk_div;
end Behavioral;

-- Correct approach uses rising_edge(clk_in) and reset signal as shown in previous examples.

Quick Reference

Tips for writing a clock divider in VHDL:

• Use a synchronous process triggered by rising_edge(clk_in).
• Include a reset signal to initialize counter and output clock.
• Toggle output clock when counter reaches half the division factor.
• Use integer counters with proper range limits.
• For odd division factors, consider more complex logic to balance high and low times.

Key Takeaways

Use a synchronous process with rising_edge(clk_in) to count input clock cycles.

Toggle the output clock after counting half the division factor to achieve frequency division.

Always include a reset to initialize the counter and output clock signal.

Avoid level-sensitive clock detection; use edge detection for reliable timing.

Handle odd division factors carefully to maintain a balanced output clock.