When to Use Blocking Assignment in Verilog: Simple Guide
= blocking assignment in Verilog when you want statements to execute in order, one after another, like steps in a recipe. It is best for combinational logic and simple procedural code where immediate updates are needed before moving to the next statement.How It Works
Blocking assignment in Verilog uses the = operator to assign values immediately and in sequence. Think of it like following a cooking recipe step-by-step: you finish one step before starting the next. This means the next line of code sees the updated value right away.
In contrast, non-blocking assignments (<=) schedule updates to happen later, like setting timers that go off after you finish all steps. Blocking assignments are simple and direct, making them ideal for tasks where order matters and you want to see changes instantly.
Example
This example shows blocking assignments used to update variables in order. Each assignment happens immediately, so the next line uses the updated value.
module blocking_example();
reg a, b, c;
initial begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
a = 1'b1; // a is set to 1 immediately
b = a; // b gets the updated value of a (1)
c = b; // c gets the updated value of b (1)
$display("a=%b, b=%b, c=%b", a, b, c);
end
endmoduleWhen to Use
Use blocking assignments when writing combinational logic or simple procedural code where each step depends on the previous one immediately. For example, in combinational always blocks (always @(*)), blocking assignments help model logic that updates instantly as inputs change.
They are also useful in testbenches for setting up signals in a clear, step-by-step way. Avoid blocking assignments in sequential logic (like flip-flops) where non-blocking assignments better represent hardware behavior and avoid timing issues.
Key Points
- Blocking assignments use
=and update values immediately. - They execute statements in order, like following steps one by one.
- Best for combinational logic and simple procedural code.
- Avoid in sequential logic where non-blocking (
<=) is preferred. - Useful in testbenches for clear, ordered signal setup.