What is Assign Statement in Verilog: Explanation and Example

In Verilog, the assign statement is used to create continuous assignments that drive values onto wires. It continuously updates the wire's value based on the expression on the right side, making it ideal for combinational logic.

How It Works

The assign statement in Verilog works like a live connection between a wire and an expression. Imagine a water pipe where the flow (value) changes instantly whenever the source changes. The wire always reflects the current value of the expression on the right side of the assign.

This means the value is continuously updated without needing a clock or trigger. It is like a real-time link that keeps the wire's value fresh as inputs change, which is perfect for describing simple logic circuits that don't store state.

Example

This example shows how to use assign to create a simple AND gate. The output wire y always reflects the AND of inputs a and b.

verilog

module and_gate(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

When to Use

Use the assign statement when you want to describe combinational logic that updates immediately as inputs change. It is ideal for simple gates, multiplexers, or any logic that does not require memory or clock control.

For example, use assign to connect signals, create logic expressions, or drive outputs that depend directly on inputs without delay.

Key Points

• Continuous assignment: assign updates the wire value all the time.
• Used with wires: It drives values onto wire types, not reg.
• Combinational logic: Perfect for logic without memory or clocks.
• Simple syntax: assign wire = expression;

Key Takeaways

The assign statement creates continuous connections that update wire values instantly.

Use assign for combinational logic that depends directly on inputs without clocks.

Assign statements only drive wire types, not registers.

It is a simple way to describe logic gates and signal wiring in Verilog.