Verilog Code for AXI Interface: Syntax, Example, and Tips

An AXI interface in Verilog uses specific signals like AWADDR, WVALID, and ARREADY to handle read/write transactions. You define these signals in a module and implement the handshake logic to communicate with AXI masters or slaves.

Syntax

The AXI interface consists of several channels: write address (AW), write data (W), write response (B), read address (AR), and read data (R). Each channel has signals for address, data, valid, ready, and response.

Key signals include:

• AWADDR: Write address
• AWVALID: Write address valid
• AWREADY: Write address ready
• WDATA: Write data
• WVALID: Write data valid
• WREADY: Write data ready
• BVALID: Write response valid
• BREADY: Write response ready
• ARADDR: Read address
• ARVALID: Read address valid
• ARREADY: Read address ready
• RDATA: Read data
• RVALID: Read data valid
• RREADY: Read data ready

These signals are declared as inputs or outputs in your Verilog module and used to implement the AXI protocol handshake.

verilog

module axi_interface_example(
    input wire ACLK,
    input wire ARESETn,
    // Write address channel
    input wire [31:0] AWADDR,
    input wire AWVALID,
    output wire AWREADY,
    // Write data channel
    input wire [31:0] WDATA,
    input wire WVALID,
    output wire WREADY,
    // Write response channel
    output wire BVALID,
    input wire BREADY,
    // Read address channel
    input wire [31:0] ARADDR,
    input wire ARVALID,
    output wire ARREADY,
    // Read data channel
    output wire [31:0] RDATA,
    output wire RVALID,
    input wire RREADY
);

// Implementation details here

endmodule

Example

This example shows a simple AXI slave interface that accepts write and read requests and stores data in a small register. It demonstrates the handshake signals and basic data flow.

verilog

module axi_slave_simple(
    input wire ACLK,
    input wire ARESETn,
    // Write address channel
    input wire [31:0] AWADDR,
    input wire AWVALID,
    output reg AWREADY,
    // Write data channel
    input wire [31:0] WDATA,
    input wire WVALID,
    output reg WREADY,
    // Write response channel
    output reg BVALID,
    input wire BREADY,
    // Read address channel
    input wire [31:0] ARADDR,
    input wire ARVALID,
    output reg ARREADY,
    // Read data channel
    output reg [31:0] RDATA,
    output reg RVALID,
    input wire RREADY
);

reg [31:0] mem_reg;

// Write address handshake
always @(posedge ACLK) begin
    if (!ARESETn) begin
        AWREADY <= 0;
    end else begin
        if (!AWREADY && AWVALID) begin
            AWREADY <= 1;
        end else begin
            AWREADY <= 0;
        end
    end
end

// Write data handshake
always @(posedge ACLK) begin
    if (!ARESETn) begin
        WREADY <= 0;
    end else begin
        if (!WREADY && WVALID) begin
            WREADY <= 1;
        end else begin
            WREADY <= 0;
        end
    end
end

// Write response logic
always @(posedge ACLK) begin
    if (!ARESETn) begin
        BVALID <= 0;
    end else if (AWREADY && AWVALID && WREADY && WVALID) begin
        mem_reg <= WDATA; // Store written data
        BVALID <= 1;
    end else if (BVALID && BREADY) begin
        BVALID <= 0;
    end
end

// Read address handshake
always @(posedge ACLK) begin
    if (!ARESETn) begin
        ARREADY <= 0;
    end else begin
        if (!ARREADY && ARVALID) begin
            ARREADY <= 1;
        end else begin
            ARREADY <= 0;
        end
    end
end

// Read data logic
always @(posedge ACLK) begin
    if (!ARESETn) begin
        RVALID <= 0;
        RDATA <= 0;
    end else if (ARREADY && ARVALID) begin
        RDATA <= mem_reg; // Return stored data
        RVALID <= 1;
    end else if (RVALID && RREADY) begin
        RVALID <= 0;
    end
end

endmodule

Common Pitfalls

Common mistakes when coding AXI interfaces include:

• Not properly implementing the handshake signals VALID and READY, causing deadlocks or missed transactions.
• Ignoring reset conditions, which can leave signals in unknown states.
• Not matching the data width between master and slave.
• Failing to handle write response BVALID and read data RVALID correctly, leading to protocol errors.

Always ensure your state machines or logic respect the AXI handshake rules and reset signals.

verilog

/* Wrong: Missing handshake for AWREADY */
// output reg AWREADY = 1; // Always ready (wrong)

/* Right: AWREADY asserted only when ready to accept address */
always @(posedge ACLK) begin
    if (!ARESETn) begin
        AWREADY <= 0;
    end else if (!AWREADY && AWVALID) begin
        AWREADY <= 1;
    end else begin
        AWREADY <= 0;
    end
end

Quick Reference

Remember these tips when working with AXI interfaces in Verilog:

• Use separate channels for read and write operations.
• Implement handshake signals VALID and READY carefully.
• Reset all control signals properly.
• Match data widths and address sizes between master and slave.
• Test your interface with AXI protocol checkers or simulation.

Key Takeaways

AXI interfaces use handshake signals VALID and READY on separate channels for reliable data transfer.

Always implement reset logic to initialize AXI signals properly.

Match data widths and address sizes between AXI master and slave modules.

Handle write response and read data valid signals to comply with AXI protocol.

Test AXI interfaces thoroughly with simulation to avoid deadlocks and protocol errors.