What is casex and casez in Verilog: Explanation and Examples

casex and casez are special case statements in Verilog that allow pattern matching with 'don't care' bits. casex treats both 'x' and 'z' as wildcards, while casez treats only 'z' as a wildcard, making them useful for matching signals with unknown or high-impedance bits.

How It Works

In Verilog, case statements compare values exactly. But sometimes, you want to ignore certain bits when matching, like when some bits are unknown or not important. This is where casex and casez come in.

casex treats both x (unknown) and z (high impedance) bits as 'don't care' bits. It means those bits can be anything and still match the case. Think of it like a pattern with wildcards that match any letter.

casez is similar but only treats z bits as wildcards, while x bits are matched exactly. This is useful when you want to ignore high impedance states but still care about unknown bits.

Example

This example shows how casex and casez match input patterns with wildcards.

verilog

module test_casex_casez;
  reg [3:0] in;
  initial begin
    in = 4'b1x0z;
    casex (in)
      4'b1xxz: $display("casex matched: %b", in);
      default: $display("casex no match");
    endcase
    casez (in)
      4'b1?0?: $display("casez matched: %b", in);
      default: $display("casez no match");
    endcase
  end
endmodule

Output

casex matched: 1x0z
casez matched: 1x0z

When to Use

Use casex when you want to ignore both unknown (x) and high impedance (z) bits in your comparisons. This is helpful in testbenches or when matching incomplete or partially unknown signals.

Use casez when you want to ignore only high impedance bits but still want to consider unknown bits as significant. This is common when dealing with tri-state buses or signals that can be driven by multiple sources.

Both are useful for writing flexible and concise pattern matching logic in hardware design.

Key Points

• casex treats both x and z as wildcards.
• casez treats only z as a wildcard, x is matched exactly.
• They help match patterns with unknown or high impedance bits.
• Useful in testbenches and designs with tri-state or incomplete signals.
• Be careful: casex can cause unintended matches if x bits are not meant to be ignored.

Key Takeaways

casex and casez allow pattern matching with 'don't care' bits in Verilog.

casex ignores both x and z bits, while casez ignores only z bits.

Use them to simplify matching signals with unknown or high impedance bits.

Be cautious with casex as it can mask unintended unknown bits.

They are helpful in testbenches and designs involving tri-state buses.