Verilog Code for Demultiplexer: Syntax and Example

A demultiplexer in Verilog routes one input to one of many outputs based on select lines using case or if-else statements inside an always block. The input is assigned to the selected output line while others are set to zero.

Syntax

The basic syntax of a demultiplexer in Verilog uses an always block triggered by changes in the select lines or input. Inside, a case statement chooses which output line gets the input value, while others are cleared.

• input: The single data input to be routed.
• select: The control lines deciding which output is active.
• output: Multiple output lines where only one carries the input at a time.

verilog

module demux(
    input wire in,
    input wire [1:0] sel,
    output reg [3:0] out
);

always @(*) begin
    out = 4'b0000; // Clear all outputs
    case(sel)
        2'b00: out[0] = in;
        2'b01: out[1] = in;
        2'b10: out[2] = in;
        2'b11: out[3] = in;
        default: out = 4'b0000;
    endcase
end

endmodule

Example

This example shows a 1-to-4 demultiplexer where a single input in is routed to one of four outputs out[3:0] based on the 2-bit select signal sel. Only the selected output line carries the input value; others remain zero.

verilog

module demux(
    input wire in,
    input wire [1:0] sel,
    output reg [3:0] out
);

always @(*) begin
    out = 4'b0000; // Reset outputs
    case(sel)
        2'b00: out[0] = in;
        2'b01: out[1] = in;
        2'b10: out[2] = in;
        2'b11: out[3] = in;
        default: out = 4'b0000;
    endcase
end

endmodule

// Testbench to demonstrate demux
module testbench;
    reg in;
    reg [1:0] sel;
    wire [3:0] out;

    demux uut(.in(in), .sel(sel), .out(out));

    initial begin
        $monitor("in=%b sel=%b out=%b", in, sel, out);
        in = 1'b1;
        sel = 2'b00; #10;
        sel = 2'b01; #10;
        sel = 2'b10; #10;
        sel = 2'b11; #10;
        in = 1'b0; sel = 2'b10; #10;
        $finish;
    end
endmodule

Output

in=1 sel=00 out=0001
in=1 sel=01 out=0010
in=1 sel=10 out=0100
in=1 sel=11 out=1000
in=0 sel=10 out=0000

Common Pitfalls

Common mistakes when coding a demultiplexer in Verilog include:

• Not resetting all outputs before assigning one, causing multiple outputs to be active.
• Using blocking assignments (=) improperly inside always blocks sensitive to multiple signals.
• Forgetting to cover all select cases, leading to latches or unintended output values.

Always initialize outputs and cover all select values to avoid glitches.

verilog

/* Wrong way: Not clearing outputs causes multiple outputs to stay high */
module demux_wrong(
    input wire in,
    input wire [1:0] sel,
    output reg [3:0] out
);

always @(*) begin
    case(sel)
        2'b00: out[0] = in;
        2'b01: out[1] = in;
        2'b10: out[2] = in;
        2'b11: out[3] = in;
    endcase
end
endmodule

/* Right way: Clear outputs before case */
module demux_right(
    input wire in,
    input wire [1:0] sel,
    output reg [3:0] out
);

always @(*) begin
    out = 4'b0000;
    case(sel)
        2'b00: out[0] = in;
        2'b01: out[1] = in;
        2'b10: out[2] = in;
        2'b11: out[3] = in;
    endcase
end
endmodule

Quick Reference

Demultiplexer Tips:

• Use always @(*) for combinational logic.
• Clear all outputs before assigning one to avoid multiple active outputs.
• Use case statements for clear select line decoding.
• Cover all select cases including default to prevent latches.

Key Takeaways

A demultiplexer routes one input to one of many outputs based on select lines using combinational logic.

Always clear all outputs before assigning the selected output to avoid multiple active outputs.

Use a case statement inside an always block triggered by select signals for clean design.

Cover all select cases including default to prevent unintended latches or glitches.

Test your demux with different select inputs to verify correct output routing.