VerilogHow-ToBeginner · 3 min read

Verilog Code for Gray to Binary Converter: Syntax and Example

A Gray to binary converter in Verilog uses bitwise XOR operations to convert each binary bit from the Gray code input. The most significant bit (MSB) of the binary output is the same as the Gray input MSB, and each following binary bit is the XOR of the previous binary bit and the current Gray bit, implemented using assign statements or procedural blocks.

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Syntax

The basic syntax for a Gray to binary converter in Verilog involves declaring input and output ports, then using bitwise XOR operations to compute the binary output from the Gray input.

The key parts are:

input [N-1:0] gray: The Gray code input vector.
output [N-1:0] binary: The binary output vector.
assign binary[N-1] = gray[N-1]: The MSB of binary equals the MSB of Gray.
assign binary[i] = binary[i+1] ^ gray[i]: Each lower bit is XOR of the next higher binary bit and current Gray bit.

verilog

module gray_to_binary #(parameter N = 4) (
    input wire [N-1:0] gray,
    output wire [N-1:0] binary
);

    assign binary[N-1] = gray[N-1];
    genvar i;
    generate
        for (i = N-2; i >= 0; i = i - 1) begin : gen_loop
            assign binary[i] = binary[i+1] ^ gray[i];
        end
    endgenerate

endmodule

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Example

This example demonstrates a 4-bit Gray to binary converter module with a testbench that applies Gray code inputs and prints the corresponding binary outputs.

verilog

module gray_to_binary #(parameter N = 4) (
    input wire [N-1:0] gray,
    output wire [N-1:0] binary
);

    assign binary[N-1] = gray[N-1];
    genvar i;
    generate
        for (i = N-2; i >= 0; i = i - 1) begin : gen_loop
            assign binary[i] = binary[i+1] ^ gray[i];
        end
    endgenerate

endmodule

module testbench;
    reg [3:0] gray;
    wire [3:0] binary;

    gray_to_binary #(.N(4)) converter(.gray(gray), .binary(binary));

    initial begin
        $display("Gray\tBinary");
        for (integer i = 0; i < 16; i = i + 1) begin
            gray = i ^ (i >> 1); // Generate Gray code from binary i
            #1;
            $display("%b\t%b", gray, binary);
        end
        $finish;
    end
endmodule

Output

Gray Binary 0000 0000 0001 0001 0011 0010 0010 0011 0110 0100 0111 0101 0101 0110 0100 0111 1100 1000 1101 1001 1111 1010 1110 1011 1010 1100 1011 1101 1001 1110 1000 1111

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Common Pitfalls

Common mistakes when writing a Gray to binary converter include:

Not assigning the MSB of the binary output directly from the Gray input MSB.
Incorrectly using XOR operations in the wrong order, which leads to wrong binary outputs.
Forgetting to use a generate loop or manually writing XOR for each bit, which is error-prone for wider buses.

Always verify the logic by testing with known Gray codes and their binary equivalents.

verilog

/* Wrong approach: XORing Gray bits directly without chaining */
assign binary = gray ^ (gray >> 1); // Incorrect for Gray to binary

/* Correct approach: Use chained XOR from MSB downwards */
assign binary[N-1] = gray[N-1];
genvar i;
generate
    for (i = N-2; i >= 0; i = i - 1) begin
        assign binary[i] = binary[i+1] ^ gray[i];
    end
endgenerate

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Quick Reference

The MSB of binary output equals the MSB of Gray input.
Each lower binary bit is XOR of the next higher binary bit and current Gray bit.
Use generate loops for scalable bit widths.
Test with known Gray codes to ensure correctness.

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Key Takeaways

The MSB of binary output is the same as the Gray input MSB.

Each binary bit is computed by XORing the next higher binary bit with the current Gray bit.

Use generate loops in Verilog for clean and scalable Gray to binary conversion.

Test your converter with known Gray code values to avoid logic errors.

Avoid incorrect XOR patterns that do not chain bits properly.