Verilog Code for D Flip Flop: Syntax and Example

A D flip flop in Verilog can be coded using an always block triggered on the rising edge of the clock. The D input is assigned to the output Q inside this block, storing the input value on each clock pulse.

Syntax

The basic syntax for a D flip flop in Verilog uses an always block sensitive to the clock's rising edge. Inside, the output Q is assigned the input D. This means on each clock pulse, the flip flop stores the value of D.

• module: Defines the flip flop block.
• input clk: Clock signal triggering the flip flop.
• input D: Data input to be stored.
• output reg Q: Output storing the data.
• always @(posedge clk): Runs code on clock's rising edge.
• Q <= D;: Non-blocking assignment storing input to output.

verilog

module d_flip_flop(
    input clk,
    input D,
    output reg Q
);

always @(posedge clk) begin
    Q <= D;
end

endmodule

Example

This example shows a simple D flip flop module and a testbench that applies clock and data signals. It demonstrates how the output Q changes to match D on each rising clock edge.

verilog

module d_flip_flop(
    input clk,
    input D,
    output reg Q
);

always @(posedge clk) begin
    Q <= D;
end

endmodule

// Testbench
module testbench();
    reg clk = 0;
    reg D = 0;
    wire Q;

    d_flip_flop uut(.clk(clk), .D(D), .Q(Q));

    // Clock generation: toggle every 5 time units
    always #5 clk = ~clk;

    initial begin
        // Apply test inputs
        #3 D = 1;  // Before first rising edge
        #10 D = 0; // Change D after first rising edge
        #10 D = 1; // Change D again
        #20 $finish;
    end

    initial begin
        $monitor("Time=%0t clk=%b D=%b Q=%b", $time, clk, D, Q);
    end
endmodule

Output

Time=5 clk=1 D=1 Q=1
Time=15 clk=1 D=0 Q=0
Time=25 clk=1 D=1 Q=1

Common Pitfalls

Common mistakes when coding a D flip flop in Verilog include:

• Using blocking assignment = instead of non-blocking <= inside the always block, which can cause simulation mismatches.
• Not using posedge clk sensitivity, causing the flip flop to update incorrectly.
• Forgetting to declare Q as reg, which is required for variables assigned inside always blocks.

Example of wrong and right assignment:

verilog

module wrong_d_flip_flop(
    input clk,
    input D,
    output reg Q
);

always @(posedge clk) begin
    Q = D; // Wrong: blocking assignment
end

endmodule

module correct_d_flip_flop(
    input clk,
    input D,
    output reg Q
);

always @(posedge clk) begin
    Q <= D; // Correct: non-blocking assignment
end

endmodule

Quick Reference

Remember these key points for a D flip flop in Verilog:

• Use always @(posedge clk) to trigger on clock rising edge.
• Assign D to Q using non-blocking assignment <=.
• Declare Q as reg because it changes inside always.
• Test with a clock signal toggling regularly.

Key Takeaways

Use non-blocking assignment (<=) inside always @(posedge clk) for correct D flip flop behavior.

Declare output Q as reg to allow assignment inside always blocks.

The flip flop captures input D on the rising edge of the clock signal.

Avoid blocking assignments (=) in sequential logic to prevent simulation mismatches.

Test your flip flop with a clock signal toggling to verify correct operation.